With lower buswidth, if all 4 channels are captured some samples are lost
With fifo size of 64, there are timing violations in the DMAC
With this configuration, 65536 samples could be captured from all 4 channels with no sample lost
Because of the DMAC destination bus is 256, the number of samples to be captured must be a multiple of 16, otherwise the system will freeze. This will be corrected in software
- removed the delay controller from the top file and added it inside the util_gmii_to_rgmii core
- removed delay related xdc constraints as they are not needed
Since we are just doing a loopback all the logic is contained within the
IO bank. By using a BUFIO instead of a BUFG we avoid having to route the
clock signal from the IO bank to the middle of the FPGA and back to the IO
bank. This reduces the skew between clock and the data signals and makes
sure that the we can use the same design over a range of different
resolutions without having to calibrate the delay.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The ADV7511 samples on the rising edge. Update the data on the falling
edge, this gives us a larger margin and improved signal stability.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Connect the raw HDMI data as generated by the ADV7604 to the ILA. For
debugging it is quite useful to be able to compare the data before and
after conversion pipeline.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
- connected reset pin, as vivado reports the reset pin erroneously
- configured XADC in simultaneous sampling mode from XAUX0 and XAUX8
- connected XADC interrupt
- because in the project constraints some base pin constraints are overwritten, the project constraints are processed late
- GPI pins were assigned instead of the XADC GIO0 and GIO1, which were assigned to the XADC for external mux mode
- removed commented code
- removed up_drp_control, up_delay_control dependencies where not needed
- added axi_jesd_gt core in the library makefile
- fixed timing tcl dependency for altera projects
Add clock rate constraints for the eth1 rx clock, otherwise the tools
assume the RX paths are unconstrained and creates a bitstream which
violates hold times which causes bit errors on the RX path.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Adrian Costina
Istvan Csomortani
Lars-Peter Clausen
Rejeesh Kutty