Commit Graph

2051 Commits (82e703df23df940fb5c409bcb3d9087a94bc00cd)

Author SHA1 Message Date
Rejeesh Kutty 6e3817d419 axi_jesd_xcvr: individual reset control 2015-07-13 10:04:34 -04:00
Rejeesh Kutty 8d6c39d307 ad9680- remove avalon streaming 2015-07-13 10:03:38 -04:00
Rejeesh Kutty c69e36314c ad9144- remove avalon streaming 2015-07-13 10:03:16 -04:00
Rejeesh Kutty 825fddd034 transceiver split up outside qsys 2015-07-10 11:45:07 -04:00
Rejeesh Kutty 8c0d74aa90 transceiver split up outside qsys 2015-07-10 11:44:42 -04:00
Rejeesh Kutty e40aac9ab6 transceiver split up outside qsys 2015-07-10 11:44:22 -04:00
Rejeesh Kutty 9d95ddc620 reset and clock additions 2015-07-09 14:29:08 -04:00
Adrian Costina 30ea87e60b fmcadc4: Set explicit PCORE_ID for AD9680 2015-07-09 19:55:58 +03:00
Adrian Costina 897c31ebbf imageon: moved spdif_rx to DMA3 to be compatible with both zc706 and zed 2015-07-09 10:58:54 +03:00
Rejeesh Kutty f1dd2435b4 signal tap removed 2015-07-08 15:47:31 -04:00
Rejeesh Kutty c9e73b023d signal tap removed 2015-07-08 15:46:52 -04:00
Rejeesh Kutty f64df40a0a signal tap removed 2015-07-08 15:47:50 -04:00
Rejeesh Kutty 19bf05c740 signal tap removed 2015-07-08 15:47:48 -04:00
Rejeesh Kutty d6d263341e signal tap needs another method 2015-07-08 15:47:47 -04:00
Rejeesh Kutty b25b2e3020 registers for signal tap 2015-07-08 15:47:45 -04:00
Adrian Costina c972779217 motcon2_fmc: updated util_gmii_to_rgmii and motcon2_fmc project for improved performance of the ethernet
- removed the delay controller from the top file and added it inside the util_gmii_to_rgmii core
- removed delay related xdc constraints as they are not needed
2015-07-08 16:23:33 +03:00
Adrian Costina b4eb7465ed library: Add missing Makefiles for axi_spdif_rx, util_jesd_align, util_jesd_xmit 2015-07-08 10:48:58 +03:00
Rejeesh Kutty bbf1c5b803 transceiver core added/gpio removed 2015-07-07 15:30:38 -04:00
Rejeesh Kutty 23428ac48b transceiver constraints for sysref 2015-07-07 15:25:36 -04:00
Rejeesh Kutty ea2bd71904 synchronize up signals separately 2015-07-07 12:51:13 -04:00
Rejeesh Kutty 075b1e5424 daq2/a10gx: added axi_jesd_xcvr control 2015-07-07 10:22:36 -04:00
Rejeesh Kutty c1fcbeec8e library/axi_jesd_xcvr: interface name matching 2015-07-07 10:21:53 -04:00
Rejeesh Kutty b106b8a8f4 library/axi_jesd_xcvr: updates 2015-07-06 13:51:55 -04:00
Rejeesh Kutty c67ca682a4 hw.tcl- added 2015-07-06 13:51:55 -04:00
Rejeesh Kutty 1cfe6fe792 axi_jesd_xcvr: initial commit 2015-07-06 13:51:55 -04:00
Rejeesh Kutty 3a5da47239 xcvr- initial checkin 2015-07-06 13:51:55 -04:00
Istvan Csomortani 46fa91d5be Makefile: Update Make files 2015-07-03 18:08:57 +03:00
Istvan Csomortani 8c98399c37 imageon_ZC706: Add axi_spdif_rx core to the design 2015-07-03 17:48:29 +03:00
Istvan Csomortani 7376218e01 axi_spdif_rx: Initial commit
NOT tested.
2015-07-03 17:46:45 +03:00
Lars-Peter Clausen 27b786e92f imageon_loopback: Use BUFIO for the HDMI clock buffer
Since we are just doing a loopback all the logic is contained within the
IO bank. By using a BUFIO instead of a BUFG we avoid having to route the
clock signal from the IO bank to the middle of the FPGA and back to the IO
bank. This reduces the skew between clock and the data signals and makes
sure that the we can use the same design over a range of different
resolutions without having to calibrate the delay.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-03 15:07:17 +02:00
Lars-Peter Clausen 02b5ce82ad imageon_loopback: Invert transmit clock
The ADV7511 samples on the rising edge. Update the data on the falling
edge, this gives us a larger margin and improved signal stability.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-03 15:07:17 +02:00
Lars-Peter Clausen 281cab091c imageon_loopback: Create a clock for hdmi_rx_clock
Create a clock for the HDMI clock to make sure that the timing paths are
properly constraint.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-03 15:07:17 +02:00
Lars-Peter Clausen 5b2877b66f imageon_loopback: Use BUFIO for the HDMI clock buffer
Since we are just doing a loopback all the logic is contained within the
IO bank. By using a BUFIO instead of a BUFG we avoid having to route the
clock signal from the IO bank to the middle of the FPGA and back to the IO
bank. This reduces the skew between clock and the data signals and makes
sure that the we can use the same design over a range of different
resolutions without having to calibrate the delay.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-03 15:06:03 +02:00
Lars-Peter Clausen f5fc3a4d2f imageon_loopback: Invert transmit clock
The ADV7511 samples on the rising edge. Update the data on the falling
edge, this gives us a larger margin and improved signal stability.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-03 15:06:03 +02:00
Lars-Peter Clausen 10cc007c57 imageon_loopback: Create a clock for hdmi_rx_clock
Create a clock for the HDMI clock to make sure that the timing paths are
properly constraint.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-03 15:06:03 +02:00
Istvan Csomortani 95500d4022 fmcomms2_rfsom: Fix GPIO connections 2015-07-03 13:03:19 +03:00
Istvan Csomortani 32ae7c771a fmcomms2_ALL: Add/fix ENABLE/TXNRX control
Add ENABLE/TXNRX control for TDD, and preserve backward compatibility for pin control with GPIOs
2015-07-03 12:55:37 +03:00
Istvan Csomortani 5208ebedd5 Revert "fmcomms2_ALL: Preserve backward compatibility for ENABLE/TXNRX control"
This reverts commit 6b15704b70.
2015-07-03 10:20:50 +03:00
Lars-Peter Clausen 88f936cc86 imageon: Put HDMI input/output FF into the IOB
This gives us predictable delays as well as very small skew between the induvidual data lines.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-02 18:36:51 +02:00
Lars-Peter Clausen 94d1792aba Revert "imageon: Connect raw data to ILA"
This reverts commit 9e4fb2d048.

This conflicts with moving the capture FF into the IOB.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-02 18:36:51 +02:00
Lars-Peter Clausen eb3a0c179b imageon: Put HDMI input/output FF into the IOB
This gives us predictable delays as well as very small skew between the induvidual data lines.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-02 18:33:32 +02:00
Lars-Peter Clausen e269fe1dd0 Revert "imageon: Connect raw data to ILA"
This reverts commit 9e4fb2d048.

This conflicts with moving the capture FF into the IOB.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-02 18:33:32 +02:00
Adrian Costina 896888d495 axi_mc_current_monitor: updated ad7401 driver to send unsigned data 2015-07-02 14:23:19 +03:00
Adrian Costina 04527f8b18 axi_mc_current_monitor: updated ad7401 driver to send unsigned data 2015-07-02 14:21:26 +03:00
Rejeesh Kutty 18e8914087 fmcjesdadc1/a5gt: pn-errors version 2015-07-01 13:43:12 -04:00
Rejeesh Kutty 35aca98b5f fmcjesdadc1/stap: added 2015-07-01 13:43:10 -04:00
Lars-Peter Clausen 3c6d19d33d axi_hdmi_tx_es: Drop strange port initializers
Those were added by mistake. It does not seem to be legal Verilog, but for
some reason Vivado accepts it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
Lars-Peter Clausen 26b0ff9853 axi_hdmi_tx: Don't accidentally send control characters in embedded sync mode
ffff and 0000 are always reserved control characters when using embedded
syncs. So make sure that we never have them in the pixel data, even when
running in full-range mode.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
Lars-Peter Clausen 6aee17da83 axi_hdmi_tx: Add control to bypass chroma sub-sampler
Add a control bit to the register map that allows to bypass the chroma
sub-sampler in the axi_hdmi_tx core. This is primarily interned to be used
to send the test-pattern directly to the HDMI transmitter without modifying
it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
Lars-Peter Clausen 68cb6df366 imageon: Connect raw data to ILA
Connect the raw HDMI data as generated by the ADV7604 to the ILA. For
debugging it is quite useful to be able to compare the data before and
after conversion pipeline.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00