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6 Commits (837b2c02e23e2e68a653624f6bd22070ae15e57e)

Author SHA1 Message Date
Adrian Costina d43ba5d26e axi_ad9963: Integrated ADC/DAC clock enables 2017-04-18 12:17:40 +02:00
Adrian Costina 3c13aa49eb axi_ad9963: Changed TX path from serdes to ddr. 
- remove delay control related logic
 2017-04-18 12:17:39 +02:00
Adrian Costina 9f8fd5c922 axi_ad9963: updated tx path 
- removed pll for power saving, added serdes circuitry instead
 2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 3e0b337eae axi_ad9963: Remove extra pipeline stages on register read path 
The register read logic is not that complicated that it needs two extra
pipeline stages. It can easily be condensed into a single combinatorial and
still meet timing with large margins.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 64dfa0432d axi_ad9963: Disable unused features of the register map 
Disable registers in the register map which are not needed for this core.
This reduces the utilization of the core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2017-04-18 12:17:39 +02:00
Adrian Costina fb945ac51c axi_ad9963: Initial commit 2017-01-31 16:18:58 +02:00