d43ba5d26e
axi_ad9963: Integrated ADC/DAC clock enables
2017-04-18 12:17:40 +02:00
3c13aa49eb
axi_ad9963: Changed TX path from serdes to ddr.
...
- remove delay control related logic
2017-04-18 12:17:39 +02:00
72cdd846b0
axi_ad9963: Allow to disable the IDELAYs on the ADC data path
...
Not all designs need the IDELAYs. Disabling them can reduce power consumption of the system.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
094872619d
axi_ad9963: Separated adc/dac clock and reset
2017-04-18 12:17:39 +02:00
9f8fd5c922
axi_ad9963: updated tx path
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- removed pll for power saving, added serdes circuitry instead
2017-04-18 12:17:39 +02:00
3e0b337eae
axi_ad9963: Remove extra pipeline stages on register read path
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The register read logic is not that complicated that it needs two extra
pipeline stages. It can easily be condensed into a single combinatorial and
still meet timing with large margins.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
fb945ac51c
axi_ad9963: Initial commit
2017-01-31 16:18:58 +02:00
Adrian Costina
Lars-Peter Clausen