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168 Commits (857ad45d579203ff883a3e31ceb4cd338f2aec88)

Author SHA1 Message Date
Rejeesh Kutty c728299e71 altera- default to latest version 2017-05-12 13:25:17 -04:00
AndreiGrozav e4ae391237 axi adc cores: Add missing ports to up_adc_common instance 2017-05-12 13:39:05 +03:00
AndreiGrozav 0e1e507541 axi dac cores: Add missing ports to up_dac_common instance 2017-05-12 13:37:34 +03:00
Rejeesh Kutty fea6eb68be up_adc_common- port name changes 2017-05-10 14:45:17 -04:00
Istvan Csomortani 85a647eda8 axi_ad9361: Fix ad_cmos_out instantiations 
This is a patch for 3627b89
 2017-04-26 10:39:54 +03:00
Istvan Csomortani 52305f74c8 altera/ad_cmos_in|out: Delete redundant parameter 2017-04-25 12:06:33 +03:00
Istvan Csomortani 3627b892c3 xilinx/ad_cmos_in|out: Delete redundant parameter 
The LVCMOS standard is a single ended IO standard. The SINGLE_ENDED
parameter is redundant in this case.
 2017-04-25 11:02:35 +03:00
Istvan Csomortani db0cd63ed3 axi_ad9361: Fix Warning[Synth 8-2611] 
In Verilog-2001 standard, redeclaration of an output port as a wire
is not allowed.
 2017-04-19 13:52:13 +03:00
Istvan Csomortani 1c23cf4621 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
Istvan Csomortani c1bdfca4c3 library: Delete all adi_ip_constraint process call 2017-04-06 12:36:47 +03:00
Istvan Csomortani c46989e4e8 Makefile: Update Makefiles for libraries 2017-03-30 18:33:22 +03:00
Istvan Csomortani 31a5c674f2 fmcomms2: Update constraints file paths 2017-03-30 16:16:02 +03:00
Istvan Csomortani ea7e93d27f fmcomms2: Use the new constriants from 335fef0 2017-03-29 18:36:09 +03:00
Rejeesh Kutty 1ef064ac03 axi_ad9361- add receive init delay 2017-03-13 16:28:38 -04:00
Rejeesh Kutty 0ae79ca7ac move/rename - delay script belongs to ad9361 2017-03-10 12:44:32 -05:00
Istvan Csomortani 6b90054343 axi_ad9361: Define CDC constraint for tdd_sync 2017-02-24 11:24:07 +02:00
Istvan Csomortani 94bda1d415 axi_ad9361: Preserve 1bit CDCs with ASYNC_REG true 2017-02-23 11:43:10 +02:00
Istvan Csomortani 2b354af876 axi_ad9361_tdd: Register the tdd_sync_cntr output 2017-02-23 11:31:23 +02:00
Adrian Costina 8ebc8fe4e2 updated makefiles 2016-12-09 23:06:41 +02:00
AndreiGrozav 9d6c93a5d8 Fix warnings 2016-11-14 15:17:15 +02:00
Rejeesh Kutty 1e0fed82f7 alt_serdes- a10 ddio fixes 2016-11-01 12:41:25 -04:00
Rejeesh Kutty 9f4c5f8060 arradio/ad9361- updates 2016-10-31 15:34:32 -04:00
Rejeesh Kutty b94cc8afb1 altera- cmos cores 2016-10-31 13:13:48 -04:00
Rejeesh Kutty cc75fa3dfe altera- java/tcl mess handling 2016-10-31 10:54:07 -04:00
Rejeesh Kutty a9d03af771 altera- serdes changes 2016-10-28 14:09:18 -04:00
AndreiGrozav 08cef5a745 axi_ad9361: Add Cyclone V SERDES support 2016-10-25 20:24:17 +03:00
AndreiGrozav 1131be91ed axi_ad9361: Makefile update 2016-10-11 23:34:13 +03:00
AndreiGrozav b7767aa18f xilinx/axi_ad9361_lvds_if: Remove ila 2016-10-11 18:13:45 +03:00
AndreiGrozav 369dad60b0 axi_ad9361: Add Altera SERDES interface support 2016-10-11 17:59:19 +03:00
AndreiGrozav 52194f0fea axi_ad9361: Add DRP connection to the interface module 2016-10-11 17:59:12 +03:00
AndreiGrozav 7194d2eccc axi_ad9361: Grup interfaces to add support for more carriers 2016-10-11 17:58:49 +03:00
Istvan Csomortani 1b9d2d434c axi_ad9361_tdd: Delete unused register 2016-10-05 17:41:08 +03:00
Istvan Csomortani 43b3761b80 axi_ad9361: Flop the tx and rx valid 2016-10-03 12:24:04 +03:00
Rejeesh Kutty b4fac96aad axi_ad9361- independent disables 2016-09-28 15:45:27 -04:00
Istvan Csomortani f7fb3ccaca axi_ad9361: Change the data path gating 
Bring up the datapath gating from the TDD controller module.
 2016-09-28 16:36:13 +03:00
Rejeesh Kutty 1a11e28821 ad9361- dac data path split 2016-09-23 16:13:46 -04:00
Rejeesh Kutty 7be6168b2e ad9361- adc data path split 2016-09-23 13:42:14 -04:00
Rejeesh Kutty 78f7384150 ad9361- vivado synthesis warnings fix 2016-09-22 13:41:18 -04:00
Istvan Csomortani 913eafed48 up_drp : Update the DRP interface to support Altera platforms 2016-09-21 15:00:45 +03:00
Istvan Csomortani 2159f78c80 axi_ad9361: Delete invalid assignment of a generated wire 2016-09-16 17:38:08 +03:00
Istvan Csomortani a183e51a12 axi_ad9361: Add parameter R1_MODE_EN 
R1_MODE_EN can disable the second I/Q channel of the core. This way
the user can save resources by cutting down the size of the core.
 2016-09-09 16:34:11 +03:00
Istvan Csomortani e42206e510 axi_ad9361: Add a TDD enable/disable parameter 2016-09-09 14:38:28 +03:00
Istvan Csomortani be41a8bcaa axi_ad9361: Delete debug ports of the tdd module 2016-09-09 14:38:28 +03:00
Rejeesh Kutty 9799599eee library/ad9361- add dac clk sel 2016-08-26 10:31:00 -04:00
Adrian Costina 6a8ca8107a common: Added common ad_dcfilter stub for altera. 2016-08-16 17:37:16 +03:00
Istvan Csomortani 0cd608a7e2 lib_refactoring: Update Make files 2016-08-08 16:38:38 +03:00
Istvan Csomortani aad8c265bc lib_refactoring: Fix path for CMOS sources 2016-08-08 15:07:54 +03:00
Istvan Csomortani df36902713 lib_refactoring: Fix path of the IO macros 2016-08-08 15:07:19 +03:00
Adrian Costina d60bce654c Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools 2016-08-05 15:16:04 +03:00
Istvan Csomortani 58b220ba81 ad_tdd_control: Add an on/off switch to the receive datapath 
For a more robust control, add an on/off switch to the receive datapath too,
in order to filter out transition noises.
 2016-08-01 11:49:27 +03:00