c728299e71
altera- default to latest version
2017-05-12 13:25:17 -04:00
cfd4e006b3
hdlmake updates
2017-04-25 15:46:26 -04:00
3627b892c3
xilinx/ad_cmos_in|out: Delete redundant parameter
...
The LVCMOS standard is a single ended IO standard. The SINGLE_ENDED
parameter is redundant in this case.
2017-04-25 11:02:35 +03:00
4f4ca84813
axi_dacfifo: Fix Makefile
2017-04-24 11:46:29 +03:00
5fe7a1b100
axi_dacfifo: Move the axi_dac_fifo_bypass module to util_dac_fifo_bypass
2017-04-21 13:23:03 +03:00
5b164ad4fa
ad_serdes_in: Fix generate block
2017-04-20 18:50:00 +03:00
faa5e3d667
ad_serdes_clk: Fix generate block
2017-04-20 18:49:00 +03:00
f0da125a4e
ad_mmcm_drp: Fix generate block
...
Can not be multiple 'if' statements inside a generate block. If there are
multiple cases use if/esle statement, but always should be one single
if/else inside a generate.
2017-04-20 18:43:37 +03:00
09ffe42603
ad_lvds_in: Allow to disable IDELAY
...
The IDELAY is not always required, but it eats up power when instantiated. Allow to disable it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
45f87b46c2
ad_lvds_in: Use "SAME_EDGE" mode
...
Currently the IDDRs are configured in SAME_EDGE_PIPELINED mode, but then
the negative data is delayed by an additional clock cycle. This is the same
behaviour as using the IDDR in SAME_EDGE mode.
Switching to SAME_EDGE mode removes extra pipelining registers while
maintaining the same behaviour.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
fc7f2ef11b
ad_serdes_out: allow selection between DDR/SDR configuration and output single ended data
2017-04-18 12:17:39 +02:00
166a4c53d5
ad_serdes_clk: allow for single ended clock input, made BUFR_DIVIDE configurable
2017-04-18 12:17:39 +02:00
1c23cf4621
all: Update verilog files to verilog-2001
2017-04-13 11:59:55 +03:00
c1bdfca4c3
library: Delete all adi_ip_constraint process call
2017-04-06 12:36:47 +03:00
8ba6012b6b
restructure: Move xilinx specific constraints to /library/xilinx/common/
2017-03-30 16:16:02 +03:00
8063ba2b66
make updates
2017-03-20 16:05:18 -04:00
7478777d8d
axi_dacfifo: Match the ports with util_dacfifo
2017-03-03 18:46:16 +02:00
3586397f57
altera/common- add asymmetric fifo
2017-03-01 15:35:04 -05:00
104e9dfcdc
adc/dac-fifo altera cores
2017-02-28 13:30:50 -05:00
11623e79be
axi_dacfifo: Fix clock for read address generation
2017-02-24 15:47:04 +02:00
3e596347fd
axi_dacfifo: Delete unused wires
2017-02-24 15:45:51 +02:00
ac2e5a9dac
constraints: Update constraints
...
Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
2017-02-24 13:43:32 +02:00
f326c03ff3
axi_dacfifo: Define constraint for bypass
...
The bypass module currently is supported, when the DMA data width
is equal with the DAC data width.
The dac_data output is enabled with dac_valid.
2017-02-24 12:35:42 +02:00
b9d3039568
axi_dacfifo: Register the dac_valid signals
2017-02-24 12:34:58 +02:00
debc6e2066
axi_dacfifo: Data from DMA is validated with dma_ready too
2017-02-24 12:32:25 +02:00
dfcd5214a0
axi_dacfifo: axi_dvalid should come from dacfifo_rd module
2017-02-24 12:28:46 +02:00
1fce57f6c3
axi_dacfifo: Redesign the bypass functionality
2017-02-23 17:32:31 +02:00
573959c826
Makefiles: fixed axi_adxcvr/util_adxcvr Makefiles to include interfaces dependancy
2017-02-23 16:16:34 +02:00
e3ac341aad
axi_dacfifo: Fix constraints
2017-02-21 14:45:18 +02:00
981a61bf16
axi_dacfifo: Clean up the axi_dacfifo_wr.v module
2017-02-17 18:40:02 +02:00
f10866e4c3
axi_*fifo: Delete/replace AXI_BYTE_WIDTH parameter
2017-02-16 19:54:41 +02:00
95a4ea20c8
axi_dacfifo: Delete redundant parameter BYPASS_EN
2017-02-16 19:53:44 +02:00
5fa6dba333
Make: Update Makefiles
2017-02-10 16:32:58 +02:00
1e54b5230f
axi_adxcvr- add m_axi associated clock
2017-02-02 11:17:56 -05:00
806d19febc
axi_adxcvr- add primitive info read
2017-02-01 13:38:29 -05:00
1c9d8c4e7c
axi_adxcvr- add primitive info read
2017-02-01 13:35:02 -05:00
d5af828b9c
Merge branch 'dev' into hdl_2016_r2
2017-01-30 17:10:05 +02:00
a2b2ebbed2
ad_lvds_in- ultrascale/ultrascale+ sim device mess
2017-01-21 20:54:21 -05:00
afcd11da87
adxcvr- add parameters for xcvr config
2017-01-19 12:40:26 -05:00
746b97dd96
xilin/axi_adxcvr: Fix clock and reset nets[C
2017-01-19 15:46:16 +02:00
d3ed417f49
axi_adxcvr: Update the packaging script to fix infer mm issues
...
- Change the clock and reset port name of the AXI slave interface
to s_axi_aclk and s_axi_aresetn. This way we can use the adi_ip_properties
process to infer the interface.
- Define an address space reference to the m_axi interface.
2017-01-19 15:16:04 +02:00
8ebc8fe4e2
updated makefiles
2016-12-09 23:06:41 +02:00
025420d6f8
library/axi_xcvrlb- xcvr changes
2016-11-23 12:00:13 -05:00
8f562fd069
xcvr updates- board procedure
2016-11-22 14:43:36 -05:00
3dbed492b3
util_adxcvr: expose cpll/qpll as it is
2016-11-22 11:32:37 -05:00
3cbe735bd8
util_adxcvr: regenerate from script
2016-11-22 11:21:04 -05:00
c57ffc9364
axi_adxcvr- separate pll reset from channels
2016-11-22 11:12:54 -05:00
b9795c7033
xilinx/util_adxcvr: Update enablement dependencies
2016-11-22 17:33:40 +02:00
9d6c93a5d8
Fix warnings
2016-11-14 15:17:15 +02:00
5731ba3300
fmcomms11- xcvr updates
2016-10-24 09:51:40 -04:00
Rejeesh Kutty
Istvan Csomortani
Lars-Peter Clausen
Adrian Costina
Istvan Csomortani
AndreiGrozav