3 Commits (857ad45d579203ff883a3e31ceb4cd338f2aec88)

Author	SHA1	Message	Date
Istvan Csomortani	f0da125a4e	ad_mmcm_drp: Fix generate block ... Can not be multiple 'if' statements inside a generate block. If there are multiple cases use if/esle statement, but always should be one single if/else inside a generate.	2017-04-20 18:43:37 +03:00
Istvan Csomortani	1c23cf4621	all: Update verilog files to verilog-2001	2017-04-13 11:59:55 +03:00
Istvan Csomortani	b806fa3b42	lib_refactoring: Move all the Xilinx common modules to library/xilinx/common	2016-08-08 15:06:10 +03:00