9caaba54d3
ad_mem_asym: Force the Xilinx synthesizer to infer Block RAMs
2020-01-13 12:25:23 +02:00
d86fbb2a08
adi_board: fixed ddr memory mapping for microblaze projects
2020-01-13 12:25:23 +02:00
53cb087b9c
ad_rst_constr: changed hier to hierarchical
2020-01-13 12:25:23 +02:00
f07652ab5a
axi_spi_engine: Add constraint for reset synchronizer
2020-01-13 12:25:23 +02:00
34ea5efdff
adi_project_xilinx: Use the latest board files
2020-01-13 12:25:23 +02:00
d2d7f2a3f9
up_clk_mon_constr: -heir is deprecated, use hierarchical instead
2020-01-13 12:25:23 +02:00
4511f731af
axi_laser_driver: Fix ip.tcl file
...
- Add a missing contraint file
- Fix the path of the ttclk file
2020-01-13 12:25:23 +02:00
87a752e242
ad_rst_constr: Search pin in all hierarchy
2020-01-13 12:25:23 +02:00
adfeb435a4
scripts: Update Vivado version to 2019.1
2020-01-13 12:25:23 +02:00
25816ac1b3
adi_project_xilinx: removed set_property SCOPED_TO_REF
2020-01-13 12:25:23 +02:00
c684c2cbd6
scripts/adi_ip_xilinx.tcl: add variable width for multi bus interfaces
...
Bus sizes often depend on parameters. In such cases the physical indexes
of the interfaces from the multi bus must be calculated based on parameters.
For each interface expose the formula that calculates the indexes to the
block design.
2020-01-13 09:55:25 +02:00
fa259c7975
ad40xx: Fix a typo
2020-01-10 10:20:06 +02:00
b93c1e6e90
intel/adi_jesd204: add bonded clock network support ( #408 )
...
* jesd204b: add bonding clocks feature (fix for some routing issues)
* intel/adi_jesd204: bonding clock feature invisible in QSYS GUI if number of lanes is less than 6
* intel/adi_jesd204: clock network option renamed according to intel documentation
* intel/adi_jesd204: Hide BONDING_CLOCKS_EN parameter in RX mode
Co-authored-by: István Csomortáni <Csomi@users.noreply.github.com>
2020-01-09 17:45:32 +02:00
9497b1cace
ad40xx: Remove redundant upscaler IP, Add timing constraints
2020-01-09 11:32:31 +02:00
3235c9189c
axi_xcvrlb: added new parameters to IP
...
added PLL locked reg to axi regmap; IP now recognizez xcvr type
automatically
2020-01-07 16:18:33 +02:00
9180d4dd39
library/axi_clkgen: Fix second clock output
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A typo prevents the usage of second clock output.
2020-01-07 13:21:00 +02:00
8db77d8f3a
ad_fmclidar1_ebz/README: Add Known Issues section
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Add description of the power-up issue and its solution.
2019-12-20 13:20:42 +02:00
d4b3a3f640
ad_fmclidar1_ebz/README: A10SOC rework guide
2019-12-18 14:47:00 +02:00
9ab4c0c783
dac_fmc_ebz: Passthrough GPIO signal for bypass
2019-12-06 11:04:45 +02:00
8b45d17eb9
dac_fmc_ebz: Only create dummy ports for unused
...
lanes
2019-12-06 11:04:45 +02:00
09ad67bfd7
adrv9009zu11eg: Make the project more parametrizable
2019-12-04 14:59:18 +02:00
2e4ac278eb
ad_fmclidar1_ebz: Add documentation
2019-12-03 18:23:57 +02:00
3c83694755
adi_fir_filter_bd.tcl: Synchronize the control GPIO input to the core clock
2019-12-03 17:27:56 +02:00
a25323b246
util_adcfifo: fix read pointer
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Read pointer should be always behind the write pointer except when it
reaches the last memory location where the writer stops.
2019-12-03 17:27:29 +02:00
82021edffe
adi_board.tcl:ad_xcvrcon: do not reorder common control
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When channels are not swapped in groups of four but are completely out of order
the common control channel can't be reordered based on the index of the
channel.
2019-11-30 12:29:32 +02:00
e6d63ec50d
util_pack: Initital support for 32 channels
2019-11-28 16:17:58 +02:00
c2726ceac9
common:vcu118: move system memory to DDR C2
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The DDR controller for C2 for is much closer to the transceivers which
connect to the FMCp connector so designs does not have to span over all
three SLRs just over two reducing implementation and timing closure effort.
2019-11-28 16:17:44 +02:00
7612b5d8dd
scripts/jesd204.tcl: add support for more lanes and converters for TPLs
2019-11-28 16:17:21 +02:00
85eabc5a08
jesd204/ad_ip_jesd204_tpl_dac: add support for more lanes and converters
2019-11-28 16:17:21 +02:00
002f8d8a3e
jesd204/ad_ip_jesd204_tpl_adc: add support for more lanes and converters
2019-11-28 16:17:21 +02:00
db573a59b0
jesd204: support for 16 lanes
2019-11-28 16:17:21 +02:00
0cb5c0bdaf
adv9009zu11eg: Update FPGA to -2. Update DDR4 clock frequency
2019-11-27 16:27:44 +02:00
c44b4957b5
ad7134_fmc/zed: Fix IO definitions for SDI lines
2019-11-27 10:04:37 +02:00
cd5848976e
axi_adc_trigger: Change out hold counter width
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Chance out hold_counter width form 17 to 20 bits.
Out hold period max ~ 20 ms. Default out hold period 2 ms.
2019-11-26 15:15:58 +00:00
4fdaa7fe12
axi_adc_trigger: Cosmetic change only
2019-11-26 15:15:58 +00:00
bdd44e37df
axi_adc_trigger: Dynamically set the out pin hold period
2019-11-26 15:15:58 +00:00
88e80f604e
daq3:zcu102: fix GPIO double drive
2019-11-26 14:41:19 +02:00
10dc090673
.gitignore: add simulation outputs and misc files to the list
2019-11-26 13:43:22 +02:00
4c2a539a96
axi_fan_control: Fixed ip version
2019-11-26 13:33:41 +02:00
8c39cf8560
scripts: adi_board.tcl: Update the axi_adxcvr to util_adxcvr connections
2019-11-26 12:57:53 +02:00
e0813d49b6
axi_adc_trigger: Fix two sample offset
...
When using a non-maximum sampling rate the data is captured earlier by two
samples.
After the initial trigger jitter fix, a low latency/utilization was
desired(one sample delay for the trigger detection). After adding the
instrument trigger an equal latency between ADC and LA was required, hence the
need for a two sample delay on the trigger path. The delay was implemented
as two clock cycle delays not two sample delays.
This commit fixes this issue and offers a more robust design.
2019-11-25 13:14:18 +00:00
d844167850
axi_adc_trigger: Fix trigger jitter
...
A trigger jitter was added by fix on the external trigger input. It
manifests at input sampling frequencies lower than the maximum frequency.
Added the required reset and CE(valid) signal to the last output
stages of the trigger to obtain the desired functionality for all
sampling rates.
2019-11-25 13:14:18 +00:00
8131c86f75
m2k: Connect the adc_trigger reset
2019-11-25 13:14:18 +00:00
ecfa6bd19d
axi_logic_analyzer: Add holdoff support
2019-11-25 13:14:18 +00:00
ede19a3b3d
axi_adc_trigger: Add holdoff support
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Add reset pin for holdoff.
2019-11-25 13:14:18 +00:00
a06c74edc7
fmcjesdadc1: Change rx_div_clk to 125MHz
2019-11-20 10:50:18 +02:00
9260979b15
adrv9364: Added sysid to all projects
2019-11-20 10:43:54 +02:00
570dae7df6
adrv9361: Added sysid to all projects
2019-11-20 10:43:54 +02:00
24b5de4438
sysid: Specified clock interface for input clk
2019-11-20 10:43:54 +02:00
dfe3258a4f
adrv9009zu11eg: Add axi_sysid
2019-11-19 10:29:57 +02:00
Istvan Csomortani
Arpadi
Laszlo Nagy
Stanca Pop
cycollineau
István Csomortáni
Prasahnt Sivarajah
Adrian Costina
AndreiGrozav