aholtzma
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2ff5420630
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Update system_top.v
Add a comment that the spi CS decoding is tied to a setting in the device tree.
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2020-11-02 16:59:08 +02:00 |
Adrian Costina
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9093a8c428
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library: Move ad_iobuf to the common library, as it's not Xilinx specific
Updated all system_project and Makefiles
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2020-11-02 16:13:35 +02:00 |
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Adrian Costina
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0644edb389
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fmcomms8: a10soc: Move RX and Observation to second SDRAM interface
This is an attempt to get full bandwidth without a FIFO
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2020-10-26 18:12:14 +02:00 |
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Adrian Costina
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6621fbec61
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fmcomms8: a10soc: Initial commit
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2020-10-26 18:12:14 +02:00 |
Sergiu Arpadi
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d8ab27b2af
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sysid: Remove cstring init string
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2020-09-30 19:12:24 +03:00 |
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Adrian Costina
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bde2d1d66d
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fmcomms8: zcu102: Leave the SPI constraint at 25 MHz
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2020-09-25 11:54:12 +03:00 |
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Adrian Costina
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4d2e05d5dd
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fmcomms8: common: In the SPI module, use ad_iobuf instead of a Xilinx primitive
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2020-09-25 11:54:12 +03:00 |
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Adrian Costina
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f8c2eb12d4
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fmcomms8: zcu102: Remove the test pins, as they are not connected
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2020-09-25 11:54:12 +03:00 |
Istvan Csomortani
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32eeedb660
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makefile: Update makefiles
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2020-05-07 08:41:49 +01:00 |
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Adrian Costina
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19b7986486
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fmcomms8: Fix SPI timing
The maximum SPI rate set to 10MHz
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2020-03-16 13:26:20 +02:00 |
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Adrian Costina
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fad52175d1
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fmcomms8: Fix spi connection
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2020-03-06 16:07:02 +02:00 |
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Adrian Costina
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50d904934a
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fmcomms8: Changed the interrupt addresses to be similar with adrv9009zu11eg project
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2020-03-06 16:07:02 +02:00 |
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Adrian Costina
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e51d9372cd
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fmcomms8: ZCU102: Added DAC FIFO
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2020-02-10 11:23:52 +02:00 |
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Adrian Costina
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016a1d540d
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fmcomms8: ZCU102: Initial commit
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2020-02-10 11:23:52 +02:00 |