Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
If the sampling clock is lower than dclk*number_of_active_lines*32 the interface should wait for the next adc_ready signal to reset the counter. The adc_valid_p signal should be set high just for a clock period after the sample was captured.
* projects/ad7768evb: Initial commit with axi_ad7768 IP * library/axi_ad7768: Initial commit for AD7768/AD7768-4