2293374307
adc|dac_fifo: Maximize the depth of each instance of the internal RAM FIFOs
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The affected projects are:
- FMCADC2/VC707 - 16Mb
- FMCADC5/VC707 - 16Mb
- DAQ2/ZC706 - ADC@1GB and DAC@8Mb
- DAQ2/KC705 - ADC@4Mb and DAC@4Mb
- DAQ2/VC707 - ADC@8Mb and DAC@8Mb
- DAQ2/KCU105 - ADC@4Mb and DAC@4Mb
- DAQ2/ZCU102 - ADC@8Mb and DAC@8Mb
- DAQ3/ZC706 - ADC@1GB and DAC@8Mb
- DAQ3/KCU105 - ADC@4Mb and DAC@4Mb
- DAQ3/ZCU102 - ADC@8Mb and DAC@8Mb
- ADRV9371x/KCU105 - DAC@8Mb
- ADRV9371x/ZCU102 - DAC@16Mb
2018-08-21 11:44:05 +03:00
fb4a583613
projects/system_bd- adc/dac fifo board designs
2017-02-27 16:06:39 -05:00
edd5e9570f
file renamed; sed output; fingers crossed
2017-02-22 15:56:37 -05:00
ce1fed1ce6
dmafifo- adc/dac split
2016-08-16 12:54:39 -04:00
15618c9edf
daq2 : Integrate the DACFIFO into the supported projects.
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+ All pack/unpack logic is made by the cpack and upack modules.
+ The DAC FIFO is integrated between the TX DMA and cpack.
+ All the top files are updated, all the projects compiled successfully.
2015-05-11 12:20:50 +03:00
6a85724793
daq2/vc707: 2014.4 updates
2015-03-26 14:02:31 -04:00
e111e1336e
conflicts-
2015-02-06 22:14:21 -05:00
e1d8dd10a9
daq2: Initial check in of the VC707 based project
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NOTE: Can not communicate with the clock chip, rx/tx PLL not locking.
2015-01-28 16:24:06 +02:00
Istvan Csomortani
Rejeesh Kutty