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3178 Commits (8845aeb6abc3505570180d42ec14be83d018087e)

Author SHA1 Message Date
Istvan Csomortani 3f3606d318 axi_ad9122: Add Altera support for the core 2016-10-24 11:43:12 +03:00
Istvan Csomortani aa46de5e5e adi_ip_alt: Add ad_generate_module_inst proc 
Add a tcl process, which can be used to generate custom module
names during the generation phase. This will be used to create
different ad_serdes_clk module, in case when independent IOPLLs are
needed for TX and RX.
 2016-10-24 11:43:00 +03:00
Istvan Csomortani 707038937a alt_serdes: Add additional parameters 
Add additional parameters to keep the top of ad_serdes_* modules
consistant through differente carriers.
 2016-10-24 11:42:43 +03:00
Rejeesh Kutty c9ac870086 usrpe31x- updates 2016-10-21 13:59:43 -04:00
Rejeesh Kutty 7b958fed87 hdlmake- updates 2016-10-21 13:59:43 -04:00
Rejeesh Kutty 48e90f0e9b usrpe31x- added 2016-10-21 13:59:43 -04:00
Istvan Csomortani 8dbfe9258f axi_ad9162: Delete duplicated port 2016-10-21 13:47:01 +03:00
Istvan Csomortani 801f980aeb adrv9371: Fix parameter name 2016-10-21 12:50:20 +03:00
Istvan Csomortani 3abd87631a fmcomms11: Fix parameter name 2016-10-21 12:49:48 +03:00
Rejeesh Kutty 0beecea02d util_adxcvr- ultrascale updates 2016-10-19 13:06:10 -04:00
Rejeesh Kutty 7db0c03a92 pzsdr1+ccbox -- updates 2016-10-19 10:32:28 -04:00
Lars-Peter Clausen 72c05e8635 axi_dmac: Fix constraints for ultrascale 
Replace "PRIMITIVE_SUBGROUP == flop" with "IS_SEQUENTIAL" as the former is
series7 specific while the later works on all platforms. This fixes the
axi_dmac timing constraints for ultrascale based platforms.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2016-10-19 14:00:54 +02:00
Adrian Costina c1b7c5e77a usb_fx3: Added FIFO on the FX3 to Zynq path, between FX3 core and DMA core 2016-10-19 09:30:51 +03:00
AndreiGrozav 17cfdd6be9 fmcomms2/a10gx: Update Makefile and qsys script 2016-10-18 12:42:14 +03:00
Istvan Csomortani ecc0addb8c scripts/adi_ip_alt.tcl: Script is case insensitive for its arguments 2016-10-18 11:25:06 +03:00
Rejeesh Kutty 918ce45e2a pzsdr1/ccbox- updates 2016-10-17 16:29:57 -04:00
Rejeesh Kutty cb97bc500a hdlmake updates 2016-10-17 16:29:57 -04:00
Rejeesh Kutty 950acaed15 ccbox- copy 2016-10-17 16:29:57 -04:00
Rejeesh Kutty bf949f1a88 axi_xcvrlb- xcvr updates 2016-10-17 16:16:57 -04:00
Rejeesh Kutty 1b3fcb5863 util_adxcvr- parameter defaults 2016-10-17 16:10:57 -04:00
Adrian Costina 7c541c704a usdrx1: ZC706, Update project to the new GT framework 2016-10-14 18:08:08 +03:00
Adrian Costina 1d1fe26624 fmcomms7: ZC706, Update project to new GT framework 2016-10-14 17:32:23 +03:00
AndreiGrozav a026d44435 axi_generic_adc: Add missing up_adc_common connections 2016-10-12 13:20:26 +03:00
AndreiGrozav b543402051 axi_mc_current_monitor: Add missing up_axi connection 2016-10-12 13:20:26 +03:00
AndreiGrozav 91995c082d axi_ad9684: Fixed up_drp_*data width 2016-10-12 13:20:26 +03:00
AndreiGrozav a505d304af Add up_dac_common missing connections 2016-10-12 13:20:26 +03:00
AndreiGrozav 43ee917d53 Add up_dac_channel missing connections 2016-10-12 13:20:26 +03:00
AndreiGrozav 1131be91ed axi_ad9361: Makefile update 2016-10-11 23:34:13 +03:00
AndreiGrozav b7767aa18f xilinx/axi_ad9361_lvds_if: Remove ila 2016-10-11 18:13:45 +03:00
AndreiGrozav 2d93d787ab altera/ad_cdfilter: Update interface to Verilog 2001 standard 2016-10-11 17:59:21 +03:00
AndreiGrozav 369dad60b0 axi_ad9361: Add Altera SERDES interface support 2016-10-11 17:59:19 +03:00
AndreiGrozav ae47895666 altera/alt_serdes: Fixed SERDES 4 factor initialization 2016-10-11 17:59:17 +03:00
AndreiGrozav d41945f568 altera/ad_serdes: Add support for any SERDES factor less than 8 2016-10-11 17:59:14 +03:00
AndreiGrozav 52194f0fea axi_ad9361: Add DRP connection to the interface module 2016-10-11 17:59:12 +03:00
AndreiGrozav 7194d2eccc axi_ad9361: Grup interfaces to add support for more carriers 2016-10-11 17:58:49 +03:00
Rejeesh Kutty 5bb77109ca daq2/a10gx- make fix 2016-10-10 13:03:44 -04:00
Rejeesh Kutty 905e29eb01 hdlmake- altera 2016-10-10 12:55:55 -04:00
Rejeesh Kutty e5cf417576 daq2/mb- xcvr procedures 2016-10-10 12:51:30 -04:00
Rejeesh Kutty 273073a584 daq2/kcu105- xcvr procedure 2016-10-10 11:12:47 -04:00
Rejeesh Kutty cc6ca4f0f2 ad_lvds_in- ultrascale sim device 2016-10-10 10:39:47 -04:00
Adrian Costina b3d3876dc5 imageon: ZC706, updated system_top to remove part of the Warnings. 
- constraints fixed so Vivado doesn't issue a Warning
 2016-10-10 17:33:42 +03:00
Adrian Costina 9efc45f0b6 imageon: Zed, updated system_top to remove part of the Warnings. 
- spi csn signals should be tied to 1 if spi is not used
- constraints fixed so Vivado doesn't issue a Warning
 2016-10-10 17:31:25 +03:00
Adrian Costina 121b341b45 axi_spdif_rx: Fixed version register issue. Added sampled_data to sensitivity list 2016-10-10 17:30:13 +03:00
Adrian Costina 8875c5bef3 fmcomms6: ZC706, updated system_top to remove part of the Warnings 2016-10-10 16:43:23 +03:00
Istvan Csomortani ff980551e6 ad_serdes: SERDES_FACTOR handover missing 
In modules ad_serdes_in/ad_serdes_out the handover of the parameter
SERDES_FACTOR did not exist, causing unwanted behavioral in case of
factors less than 8.
SERDES_FACTOR must be hand over to DATA_WIDTH parameter of the SERDES
primitive.
 2016-10-10 16:38:42 +03:00
Istvan Csomortani f34aa67029 axi_hdmi: Fix a typo 2016-10-10 16:22:18 +03:00
Istvan Csomortani fcd56a2f90 daq3/a10gx: Update project to the new GT framework 
- Update common script
- Update system_top, some port names were changed
- Update constraint files
 2016-10-10 16:22:08 +03:00
Istvan Csomortani 15f36af4c2 axi_ad9152: Update core to support Altera platforms 2016-10-10 16:21:49 +03:00
Adrian Costina 94f55f20e9 adv7511: KCU105, updated system_top to remove part of the Warnings 2016-10-10 16:12:17 +03:00
Adrian Costina f464497062 cn0363: Microzed, updated system_top to remove part of the Warnings 2016-10-10 16:08:59 +03:00