fd0870352b
ad9081_fmca_ebz_x_band:zcu102: X band project initial version
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HDL project for Stingray: X/Ku Band Phased Array Prototyping System
2022-10-18 09:21:14 +03:00
fdb829347a
ad9083 based projects: Expose JESD parameters
2022-10-12 17:50:17 +03:00
67a5737fa1
ad9083_vna: Init commit
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Compatible with RevB
2022-10-10 17:32:17 +03:00
28ace647d1
up_adc_common: Update IPs and adi_regmap_adc definition file to latest up_adc_common module
2022-10-05 14:56:36 +03:00
5008999bea
up_adc_common: Add register data reading/writing functionality
2022-10-05 14:56:36 +03:00
775a23ebf2
up_adc_channel: Update IPs and adi_regmap_adc definition file to latest up_adc_channel module
2022-10-05 14:27:51 +03:00
045327c8db
common/up_adc_channel: Add raw data reading functionality
2022-10-05 14:27:51 +03:00
1eb5f4985b
projects/common: Add build files templates carriers. Modified Quartus Versions
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The build files are available for the following carriers:
* intel: a10gx, a10soc, c5soc, de10nano, s10soc
* xilinx: coraz7s, kc705, kcu105, vc707, vc709,
vck190, vcu118, vcu128, vmk180,
zc702, zc706, zcu102, zed
* Added Makefiles, system_constr.sdc, system_qsys intel
* Added Makefiles, system_bd, system_constr xilinx
* de10nano, c5soc: Changed quartus version from 20.1.1 to 21.1.0
according to last commit update
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2022-10-05 10:47:21 +03:00
a4e052e986
cn0506: Update project's directory name in the README file
2022-10-03 10:30:24 +03:00
5350baffd0
adrv9009zu11eg/common/adrv9009zu11eg_bd: Add logic for TX_JESD_L=4
2022-10-03 10:27:33 +03:00
a95536973f
adrv9009/common/adrv9009_bd: Add logic for TX_JESD_L=2
2022-10-03 10:27:33 +03:00
6a583a8ace
projects/fmcomms8: Expose jesd params, add support for TX_JESD_L=4
2022-10-03 10:27:15 +03:00
56691bd440
projects/cn0501: Updated with axi_ad7768 IP for Coraz7s
2022-09-30 12:56:57 +03:00
9caa15522a
The memory interconnect was moved from HP0 to HP1 on Coraz7s projects ( #1023 )
2022-09-29 15:14:57 +03:00
880f37555f
ad719x_asdz/coraz7s: Initial commit
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* Added interrupt on RDYn on GPIO 32
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2022-09-28 16:30:42 +03:00
19c76d1d4f
run_tb.sh:don't run xsim if previous commands fail
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If 'xvlog' or 'xelab' xilinx commands are failing, exit from
run_tb.sh script without trying to run simulation.
Signed-off-by: stefan.raus <stefan.raus@analog.com>
2022-09-28 14:25:21 +03:00
8960652c5a
library/jesd204/ad_ip_jesd204_tpl_adc: Added support for PN7 and PN15 ( #1019 )
2022-09-28 13:07:36 +03:00
56290a609d
ad4630_fmc: Match project name with folder name
2022-09-26 15:37:49 +03:00
d2d32458f4
ad9783_ebz: Match project name with folder name
2022-09-26 15:37:49 +03:00
3e297f54dd
projects/adrv9009zu11eg: expose jesd params to make and add FMCOMMS8 parameter
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Expose JESD parameters to make.
Add FMCOMMS8 parameter.
Changed the name of the observation path to match the rest of the repo.
Replace old dac_data_width formula with a more generic one.
2022-09-26 14:26:31 +03:00
88f48cba61
library/scripts/library.mk: clean files form tb
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Update clean command to delete also files generated by simulation,
from 'tb' folders, covering cases for Xsim and ModelSim simulators.
Signed-off-by: stefan.raus <stefan.raus@analog.com>
2022-09-26 13:09:21 +03:00
8a77d4fb05
coraz7s: Memory interconnect fix ( #1014 )
2022-09-23 14:58:43 +03:00
542c361e0a
docs/regmap: Added ADI regmap_*.txt files ( #1008 )
2022-09-21 15:12:35 +03:00
f3f4686759
axi_ltc2387: Update up_adc_common and up_adc_channel instances
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* Cosmetic changes also
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-09-21 09:42:40 +03:00
bc94402b91
axi_ltc2387: Make adc_valid to represent the current sample
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* Before, adc_valid was for the previous sample. This said that
at the second rising edge of clk_gate - the first sample is valid,
which is not true
* Alongside with the software issue that will be solved, these fixes
will make the first 2 samples to be with valid data, otherwise the
user has to always keep in mind that the first 2 ones are invalid
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-09-21 09:42:40 +03:00
474b8d5bed
cn0577/zed: Update xdc to diff_term true. Disable csn in system_top
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* Update xdc to use diff_term true instead of diff_term 1
* Generated xdc using adi_fmc_constr_generator.tcl
* Make CSN to be inactive
* Cosmetic changes also
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-09-21 09:42:40 +03:00
6b94259a52
projects/common: Add system_top _project templates
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Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
projects/common: Correct code and modify according to guidelines
* Added spacing to ports declaration
* Corrected coding mistakes/misspelling
* Modified/added variables names
* Added seetings (intel) and removed specific optimization settings
* Added assignments to unassigned pins (gpios)
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
projects/common: Correct/Add missing wrapper ports and iobufs
* Added port in wrapper (mainly spi) according to base design file
* Added instances of iobufs where missing
* Corrected gpio assignments or added missing ones
* Corrected minor guidelines mistakes
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
ac701/system_top.v: Change top based on previous projects
* Looked at fmcomms1, fmcomms2 from hdl_2016_r1 and datasheet
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
projects/common: Modify templates to build without errors
* Changed path for adi_env.tcl
* Moved adi_project command before assign intel
* Removed unnecessary spi signals
* Added spi ports with default logic
* a10soc: Removed pl-ddr signals and ports
* ac701: system_bd: Modified mdio interface
system_project: Added adi_board, adiobuf sourcing
system_top: Removed hdmi, i2c, fanpwm, spdif ports
according to base design
* c5soc: Added version settings
Removed unused gpios
* microzed: system_bd: Enabled RTS1 to use FCLK
system_top: Removed hdmi, i2c, unused gpios
* vc709: Separated input from ouput gpio, according to bd
Removed unnecessary ports
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
projects/common: Delete microzed vmk_es templates
* Removed hp0 interconnect from cora base design
* Added extra line to files de10nano
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2022-09-20 17:00:49 +03:00
b02f437110
docs: Add common template for evaluation board specific fmc files
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Instructions to use the template are found on the first page of the template
Signed-off-by: AndrDragomir <andrei.dragomir@analog.com>
2022-09-20 14:11:08 +03:00
7cde7cd048
projects/scripts: Add fmc constraints generator script
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Using the script:
- make sure that the eval board in use has a common fmc connection file.
if you created a new one, it should be saved as &project_name_fmc.txt inside
&project_name/common
- open a tcl terminal, either inside or outside the project
- make sure your current directory is &hdl_repo/projects/&project_name/&carrier
- source the script found at &hdl_repo/project/scripts/fmc_constr_generator.tcl
- call gen_fmc_constr $parameter_1 $parameter_2:
- in case of only one fmc port on the carrier call without any parameters
- if there are two fmc ports on the carrier and you want to use only one,
the first parameter should contain an indication (fmc_lpc/hpc, fmc0/1, etc.)
- if there are two fmc ports on the carrier and you want to use both, then
both parameters should contain an indication
- the constraints file will be generated in the current directory
Signed-off-by: AndrDragomir <andrei.dragomir@analog.com>
2022-09-20 14:11:08 +03:00
72378a6d4a
projects: Add fmc connection files for eval boards
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Creating a new eval board fmc file:
- docs: Open FMC_eval_board_template.xlsx
- follow the instructions on the first sheet
2022-09-20 14:11:08 +03:00
72cf8f9b5d
projects/common: Add fmc connection files for every platform
2022-09-20 14:11:08 +03:00
158c10df34
projects: starndadize the jesd make parameters
2022-09-13 11:53:21 +03:00
b1bf17d574
scripts/check_readme: Change search to be case insensitive
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2022-09-01 13:43:25 +03:00
8905147698
common/tb/ad_pack_tb: Add non random scenario as first test for easier debug
2022-08-25 12:35:59 +03:00
d20e604864
ad9082_fmca_ebz/zcu102: Make TPL width overwritable
2022-08-25 12:35:42 +03:00
ee3af4c9c6
axi_jesd204: Cleanup unused parameter
2022-08-25 12:35:42 +03:00
a1d31b4913
axi_jesd204_rx/jesd204_up_rx: Set buffer delay in beats of device clock
2022-08-25 12:35:42 +03:00
e332409610
ad9081_fmca_ebz: Make TPL width overwritable
2022-08-25 12:35:42 +03:00
5c86c15ff3
library/jesd204: Add support for a gearbox ratio in which the TPL width is smaller than the PHY interface
2022-08-25 12:35:42 +03:00
567be16bf6
library/jesd204: Update the script which computes the TPL width to be able to assign custom values
2022-08-25 12:35:42 +03:00
5a06f186ae
ad9081_fmca_ebz/common: Use the script to compute the TPL width
2022-08-25 12:35:42 +03:00
f955fbc6c0
adi_pd.tcl: Fix sysid branch string
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For some newer versions of git where by default color.ui=always.
The colored string captured can result in some special characters
(ASCI escape codes for coloring the terminal output) before and after the string.
e.g:
$ git branch > test.txt
$ vim test.txt
"
* ^[[32mmaster^[[m
dev_new_device^[[m"
The above escape codes will mess up a terminals color scheme when this
information is read from sysid and displayed on a terminal.
Use --no-color flag to fix this issue.
2022-08-25 11:36:25 +03:00
388611866a
projects: Fix some Makefiles
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* ad9082_fmca_ebz/vcu118
* dac_fmc_ebz/vcu118
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-08-25 09:35:55 +03:00
cf4e1b79cf
scripts:adi_env: Change the default version of Quartus Standard to 21.1 ( #996 )
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New version of Quartus Standard for de10nano and sockit was changed
to 21.1.
Signed-off-by: Liviu Adace <liviu.adace@analog.com>
Signed-off-by: Liviu Adace <liviu.adace@analog.com>
2022-08-24 17:01:06 +03:00
cc18f90579
Added axi_ad7768 IP Core ( #989 )
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* projects/ad7768evb: Initial commit with axi_ad7768 IP
* library/axi_ad7768: Initial commit for AD7768/AD7768-4
2022-08-24 16:57:14 +03:00
a824bbfdbe
library/scripts/adi_ip_xilinx.tcl: remove duplicate adi_env.tcl source
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Signed-off-by: LIacob106 <liviu.iacob@analog.com>
2022-08-23 17:55:27 +03:00
4307e3071f
scripts:adi_env: Change the default version of Quartus Pro to 21.4 ( #988 )
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New version of Quartus Pro for A10SOC, A10GX and S10SOC was changed
to 21.4. Is known that some projects will not build anymore due to
timming violations.
2022-08-18 17:08:29 +03:00
e02d31cdfd
scripts: Set required Vivado version only in adi_env.tcl
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Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-08-18 15:41:58 +03:00
dde37124a4
scripts: Update Vivado version to 2021.2
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Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-08-18 15:41:58 +03:00
214cf5896e
library/common: Enable automatic logging of simulation output
2022-08-10 12:00:15 +03:00
Laszlo Nagy
AndreiGrozav
alin724
laurent-19
Liviu.Iacob
PopPaul2021
PopPaul2021
Iulia Moldovan
stefan.raus
Stanca Pop
AndrDragomir
Ionut Podgoreanu
ladace