58e0044643
axi_adc_trigger: Use valid in data delay stage
...
This is required to match the delays in the data path to internal/external
trigger path.
2020-08-13 07:01:19 +03:00
4766d01915
m2k: Update constraints
2020-08-13 07:01:19 +03:00
4d39a3595f
m2k: Connect signals for instrument sync
2020-08-13 07:01:19 +03:00
c797a2e14f
axi_adc_decimate: Export signals indicating the rate
...
- oversampling_en signal
- filter mask value
Those signals will be used by the axi_adc_trigger.
2020-08-13 07:01:19 +03:00
2e0ba5bffd
axi_logic_analyzer: Auto sync to ADC path
...
The number of delay taps in the LA data path can be controlled manually, from
the regmap or automatically, according to the axi_adc_decimate's rate.
Moreover, because the rate is configure by software, and the time of
initialization, is different for the ADC path and LA path. There is an
uncertainty of plus/minus one sample between the two. Because ADC and LA
paths share the same clock we can easily synchronize the two paths. We
can't use reset, because the rate generation mechanism is different
between the two. So the ADC path is used as master valid generator and we
can use it to drive the LA path.
The synchronization is done by setting the rate source bit. This
mechanism can only be used if the desired rate for both path is equal,
including oversampling fom ADC decimation.
2020-08-13 07:01:19 +03:00
d2b1164567
axi_dmac: Add interface description register
...
Adds information on:
- Log 2 of interface data widths in bits
- Interface type (0 - Axi MemoryMap, 1 - AXI Stream, 2 - FIFO ) .
Lets the driver discover interface widths and interface type settings,
this will deprecate the corresponding device tree properties.
This is useful in case of parametrized projects where the width of
the datapath is changing. This change will allow the use of a generic
device tree node.
Updated version to 4.3.a
2020-08-12 17:50:16 +03:00
f3b69c15c9
scripts/intel: Update version check
2020-08-12 10:33:29 +03:00
218f45a0df
scripts/intel: Set supported Quartus version to 19.3
2020-08-12 10:33:29 +03:00
04fed45e54
util_cpack2: support for 64 channels
2020-08-11 10:37:59 +03:00
b49928fca6
ad_ip_jesd204_tpl_adc: add support for 64 channels
2020-08-11 10:37:59 +03:00
2ca09adaf7
ad_ip_jesd204_tpl_dac: expand address space to accomodate 64 channels
2020-08-11 10:37:59 +03:00
59c2e581a2
util_upack2: support for 64 channels
2020-08-11 10:37:59 +03:00
e698b286e5
jesd204: DAC TPL to support 64 channels
2020-08-11 10:37:59 +03:00
62eb5a067d
fmcomms2/a10soc: Unused outputs should be left hanging
2020-08-11 10:14:18 +03:00
fe90fc7e57
axi_ad9361: add_instance command must have a version attribute
2020-08-11 10:14:18 +03:00
a66029aef3
adrv9009/a10gx: Delete redundant timing constraints
2020-08-11 10:14:18 +03:00
02ada3bbf7
a10gx: Delete input/output delay definitions
...
All input and output delays should be referenced to a virtual clock.
If the input and output delays reference base clocks or PLL clocks rather than
virtual clocks, the intra- and inter-clock transfer clock uncertainties,
determined by derive_clock_uncertainty, are incorrectly applied to the I/O ports.
See mnl_timequest_cookbook.pdf for more info.
2020-08-11 10:14:18 +03:00
f1a0946a5d
daq3: Delete redundant timing constraint
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Delete none generic timing constarints related to the memory interface.
Set optimization mode to default.
2020-08-11 10:14:18 +03:00
1c907b9248
daq2/a10gx: Use the default optimization mode
2020-08-11 10:14:18 +03:00
9043f3737b
Revert "a10gx: Optimise the base design"
...
This reverts commit 9afc871b70
2020-08-11 10:14:18 +03:00
4af0c98c56
a10gx: Fix exceptionSlave interface definition for HPS
2020-08-11 10:14:18 +03:00
5ba3448987
scripts/project-intel: Update CLEAN target
2020-08-11 10:14:18 +03:00
0b51c474a1
a10gx: Add a Avalon Pipeline Bridge between EMIF and DMA's
2020-08-11 10:14:18 +03:00
0c7d85ac87
axi_laser_driver: Fix IP paramtere editor error
...
The parameter property 'type' cannot be modified after
adding the parameter.
2020-08-11 10:14:18 +03:00
6d19041b21
dac_fmc_ebz: QPRO is using apply_instance_preset
2020-08-11 10:14:18 +03:00
f38b9d44b9
util_adcfifo: Update the interfaces for the asymetric memory
2020-08-11 10:14:18 +03:00
f624d5df40
intel_mem_asym: Update the interface definitions
...
The ram_2port IP has different interface names in Quartus PRO and
Quartus Standard.
Update the interface names for the support Quartus PRO.
2020-08-11 10:14:18 +03:00
2198320981
intel_mem_asym: add_instance command must have a version attribute
2020-08-11 10:14:18 +03:00
0de5039b96
avl_dacfifo: add_intance command must have a version attribute
2020-08-11 10:14:18 +03:00
3e6d9ee019
adi_jesd204: Delete redundant connections
2020-08-11 10:14:18 +03:00
e856a99e49
adi_jesd204: add_instance command must have a version attribute
2020-08-11 10:14:18 +03:00
8fd1ad64d6
quartus: Increase tool version to 19.2
2020-08-11 10:14:18 +03:00
f3142a6a7a
adi_project_intel: set_interconnect_requirment command is deprecated
...
Use set_domain_assignment to set up the maximum pipeline stages for the
main interconnect.
2020-08-11 10:14:18 +03:00
a39fa831d0
ad9371:a10gx: Relax interconnect requirements
2020-08-11 10:14:18 +03:00
7e22f91429
adrv9371:a10gx: Remove constraint from DDR
2020-08-11 10:14:18 +03:00
359e5d94ec
a10gx: Remove constraint from eth_ref_clk
2020-08-11 10:14:18 +03:00
967a138d0f
adi_project_intel: Add support for Quartus Pro
...
By defualt the supported tool chain is Quartus PRO. If you want to
build the project with Quartus Standard, you need to define an environment
variable called QUARTUS_PRO_ISUSED with the value 0. (e.g. export
QUARTUS_PRO_ISUSED=0 )
Note: Not all projects going to build on Quartus Standard, you should
fix the errors if there is any.
2020-08-11 10:14:18 +03:00
054193e083
adi_project_intel: Delete all MESSAGE_DISABLE assignment
...
These kind of assignments should be placed into file like
~/projects/scripts/adi_xilinx_msg.tcl
2020-08-11 10:14:18 +03:00
4ca1311d57
quartus_pro: Global assignment ENABLE_ADVANCED_IO_TIMING is not supported
2020-08-11 10:14:18 +03:00
53e07c5d29
quartus_pro: Parameter property TYPE is not supported
2020-08-11 10:14:18 +03:00
8d6b8fc631
Add cn0506_rmii/zcu102 support on revB
2020-08-10 18:32:44 +03:00
7e96514230
Add cn0506_rmii/zc706 support on revB
2020-08-10 18:32:44 +03:00
321b82398b
Add cn0506_rmii/zed support on revB
2020-08-10 18:32:44 +03:00
9122d98132
adi_intel_device_info_enc.tcl: Fix typo
2020-08-10 18:30:46 +03:00
4e438261aa
ad_serdes_out: Add CMOS support
2020-08-07 08:31:19 +03:00
837475db0d
ad_serdes_in: Add CMOS support
2020-08-07 08:31:19 +03:00
e6b9e21ad1
ad_serdes_out: Add tristate option
2020-08-07 08:31:19 +03:00
c5c772127d
up_delay_cntrl:ad_serdes_in: Make delay value width parametrizable
...
US/US+ devices have IDELAY/ODELAY with 512 taps. This requires wider
control value for delay selection. 9 bits contrary to 5 on 7series.
2020-08-07 08:31:19 +03:00
37d378c753
common/ad_serdes_out.v: Add US/US+ support
2020-08-07 08:31:19 +03:00
65d39b9164
common/ad_serdes_in.v: Add US/US+ support
2020-08-07 08:31:19 +03:00
AndreiGrozav
Laszlo Nagy
Istvan Csomortani