zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
6,260 Commits
1 Branch
0 Tags
23 MiB
Commit Graph

12 Commits (88f48cba619f281fc2b2f4102ad309391e9fa5ab)

Author SHA1 Message Date
Iacob_Liviu 482f0489a3 scripts: Merge adi_env.tcl into a single file 
Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
 2022-08-08 13:52:54 +03:00
Iulia Moldovan 961ebe0cc2 projects: Update .v files according to guideline 
Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
 2022-06-28 18:06:56 +03:00
Robin Getz 63b6711cfa start adding some doc to the ./projects directory 
This adds a Readme.md to each project directory with pointers to project
documentation in the wiki, and the drivers (if they exist). This will
help with some autogenerated doc in the wiki, that is generated with the
innovatily named "wiki_summary.sh" shell script that parses through
these Readme.md files, and generates a summary table.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Iacob Liviu Mihai <liviu.iacob@analog.com>
 2021-11-10 14:01:06 +02:00
Adrian Costina 591a23156b Makefiles: Update header with the appropriate license 2021-09-16 16:50:53 +03:00
sergiu arpadi 7b7609d21a ad469x: Clean system_project.tcl 2021-06-03 15:41:58 +03:00
Sergiu Arpadi 6a374ef457 ad469x/zed: Add multicycle path constraint 2021-03-22 13:05:05 +02:00
sergiu arpadi acbbd4636a sysid: Upgrade framework, header/ip are now at 2/1.1.a 
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
 2021-01-20 01:02:56 +02:00
Adrian Costina 9093a8c428 library: Move ad_iobuf to the common library, as it's not Xilinx specific 
Updated all system_project and Makefiles
 2020-11-02 16:13:35 +02:00
sergiu arpadi 7cc5716ea8 ad469x: Remove sysid custom string init 2020-10-28 11:31:50 +02:00
sergiu arpadi 5359d991b2 ad469x_zed: Update bd.tcl with new port names 2020-10-28 11:31:50 +02:00
Istvan Csomortani ad4adddbe5 ad469x_fmc: Minor cosmetic update on the config file 2020-10-27 10:09:50 +02:00
sergiu arpadi 35e4eb6a7b ad469x: Add reference design for ad469x eval board 2020-10-22 19:17:10 +03:00