zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
6,260 Commits
1 Branch
0 Tags
23 MiB
Commit Graph

7 Commits (88f48cba619f281fc2b2f4102ad309391e9fa5ab)

Author SHA1 Message Date
Laszlo Nagy 78333b2c90 ad9081_fmca_ebz/common/versal_transceiver: Separate lane rates for Tx and Rx 2022-08-04 09:52:57 +03:00
Laszlo Nagy 80b3fc2d0a ad9081_fmca_ebz: versal: Remove unused GT reset input pin 
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
 2021-11-22 16:18:29 +02:00
Laszlo Nagy 0b9631f1f7 ad9081_fmca_ebz: versal: Rename nets 2021-11-19 14:01:48 +02:00
Laszlo Nagy ca6248ba88 ad9081_fmca_ebz/common/versal_transceiver.tcl: Reset also PLL 2021-11-19 14:01:48 +02:00
Laszlo Nagy 731ed0a7a5 ad9081_fmca_ebz/vck190: Updated to hierarchical versal transceiver 
Vivado cannot nest multiple block designs than two layers. This makes
replication of designs difficult.

Create a hierarchy around the Versal transceiver that includes also the
converters, this type of interface would match the util_adxcvr
interface.

Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
 2021-11-19 14:01:48 +02:00
Laszlo Nagy 1d951cfbae ad9081_fmca_ebz/vck190: Change default profile to 2 lanes 2021-11-19 14:01:48 +02:00
Laszlo Nagy 6c58a8d1ab ad9081_fmca_ebz/common: Add Versal transceiver support 2021-10-05 14:09:51 +03:00