Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
For CMOS case, lane rates are so low that reference clock of the source
synchronous interface can be routed on non-clock routes. The delays on
the clock line are adjusted by the digital interface tuning controlled
through software.
Lock down clock buffers on Rx and Tx interfaces, this avoids suboptimal
placement which causes large skew between clocks at the serdes pins.
1. Reduce max allowed skew between source synchronous clocks that can
occur due PCB differences. 250ps represents a difference more than an
inch.
2. In order to reduce skew between source synchronous clock and the
divided clock instruct the tool to use a common clock root for them.
Iacob_Liviu
Iulia Moldovan
Laszlo Nagy
Adrian Costina
Sergiu Arpadi