Commit Graph

84 Commits (890569d53fc08e52a7a084e864b4fd268ba2fffe)

Author SHA1 Message Date
Iulia Moldovan db94628cc6 library & projects: Update Makefiles
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-01-27 11:54:05 +02:00
Ionut Podgoreanu 5b95b6ce1f ad9081_fmca_ebz: Integrate the new TDD in project 2022-12-13 16:26:02 +02:00
AndrDragomir 8b9175a80c projects: Fix intermitent timing violation on a10soc
adrv9009, dac_fmc_ebz, ad9081_fmca_ebz, fmcomms8:
Increased PLACEMENT_EFFORT_MULTIPLIER global parameter to 1.2 for increased quality of placement
2022-12-13 14:21:24 +02:00
Bogdan Luncan 72313df81f Updated the makefiles to build the projects in subdirectories based on the build parameters.
Running 'make' will build the default project directly in the project folder (like it did before)
Running 'make RX_LANE_RATE=15 TX_LANE_RATE=15' will build the project inside the 'RXRATE15_TXRATE15' subdirectory.
Running 'make CFG=cfg/test_config.txt" will use the variables found inside the configuration file and build the project inside the 'test_config' subdirectory.
Running 'make clean' will clean the default project only.
Running 'make CFG=cfg/test_config.txt clean' will clean the 'testconfig' build.
Running 'make clean-all' will delete all the built configurations and libraries.

Note that the 'JESD' and 'LANE' words from the parameter names are stripped.

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
2022-11-14 09:38:42 +02:00
LIacob106 158c10df34 projects: starndadize the jesd make parameters 2022-09-13 11:53:21 +03:00
Laszlo Nagy e332409610 ad9081_fmca_ebz: Make TPL width overwritable 2022-08-25 12:35:42 +03:00
Ionut Podgoreanu 5a06f186ae ad9081_fmca_ebz/common: Use the script to compute the TPL width 2022-08-25 12:35:42 +03:00
Iacob_Liviu 482f0489a3 scripts: Merge adi_env.tcl into a single file
Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-08-08 13:52:54 +03:00
Laszlo Nagy d48b1bcdce ad9081_fmca_ebz/vck190: Expose ref clock parameter 2022-08-04 09:52:57 +03:00
Laszlo Nagy 78333b2c90 ad9081_fmca_ebz/common/versal_transceiver: Separate lane rates for Tx and Rx 2022-08-04 09:52:57 +03:00
Laszlo Nagy 2b274f945f ad9081_fmca_ebz: Reset cpack with Rx data offload 2022-08-01 12:47:26 +03:00
Iulia Moldovan 961ebe0cc2 projects: Update .v files according to guideline
Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
Laszlo Nagy 171daab8f2 ad9081_fmca_ebz: a10soc: Update resistor change comment
A board rework is required so the clocks, chip selects or sync signal reach the part correctly.  Without this the link will not come up.
2022-06-21 14:19:58 +03:00
Laszlo Nagy bdd5686e95 ad9081_fmca_ebz/a10soc: Make second sync CMOS and GPIO controllable 2022-05-26 09:13:05 +03:00
Laszlo Nagy a2da965391 ad9081_fmca_ebz/vck190: Make second sync CMOS and GPIO controllable 2022-05-26 09:13:05 +03:00
Laszlo Nagy 20b89ddd99 ad9081_fmca_ebz/vcu128: Make second sync CMOS and GPIO controllable 2022-05-26 09:13:05 +03:00
Laszlo Nagy b3d231e569 ad9081_fmca_ebz/zc706: Make second sync CMOS and GPIO controllable 2022-05-26 09:13:05 +03:00
Laszlo Nagy 044017e0b9 ad9081_fmca_ebz/zcu102: Make second sync CMOS and GPIO controllable 2022-05-11 18:09:08 +03:00
Laszlo Nagy 97b92565b2 Makefile: Replace util_fifo2axi_bridge with util_hbm 2022-04-28 14:31:32 +03:00
Laszlo Nagy fa168fafe0 ad9081_fmca_ebz:vcu128: Disable offload bypass
The internal bypass FIFO has poor timing performance,
when using HBM data can be passed always through the external memory
without storage length constraints, so no need for the internal bypass FIFO.
2022-04-28 14:31:32 +03:00
Laszlo Nagy c57015f80e ad9081_fmca_ebz/vcu128: Use HBM for data offload cores 2022-04-28 14:31:32 +03:00
Laszlo Nagy dbadb9eb61 ad9081_fmca_ebz/common: Make data offload memory type selectable
Make the storage type over writable so it can be set specifically
to carriers.

Address width of external memory AXI master is calculated in the
interfacing core (util_hbm) so that parameters is removed.
2022-04-28 14:31:32 +03:00
David Winter 638491d502 projects: ad9081: Disable tdd_sync CDC sync of TDD controller
Signed-off-by: David Winter <david.winter@analog.com>
2022-04-20 10:54:53 +03:00
Laszlo Nagy 8df1d8eade ad9081_fmca_ebz: Update parameter description 2022-03-11 13:16:22 +02:00
Laszlo Nagy 45dae0f3d3 ad9081_fmca_ebz/common: Connect sync at TPL level
Reset CPACK from ADC TPL so during armed capture clear the cpack to avoid
capturing old samples.
Reset UNPACK with TPL to clear upack during armed transfers to avoid
sending old data.
2022-02-07 19:14:01 +02:00
Dan Hotoleanu 77f3e5155b ad9081_fmca_ebz: Fix signal length parameter
Corrected the length parameter for the rx_data input.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-12-08 14:29:48 +02:00
Laszlo Nagy 80b3fc2d0a ad9081_fmca_ebz: versal: Remove unused GT reset input pin
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-11-22 16:18:29 +02:00
Laszlo Nagy 1ec0993d33 ad9081_fmca_ebz/vcu128: Remove ref clock replica
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-11-22 16:18:29 +02:00
Laszlo Nagy e76f287e73 ad9081_fmca_ebz:vcu128: Initial version
* 4Txs / 4Rxs per MxFE
 * Tx I/Q Rate: 250 MSPS
 * Rx I/Q Rate: 250 MSPS
 * DAC JESD204B: Mode 9, L=4, M=8, N=N'=16
 * ADC JESD204B: Mode 10, L=4, M=8, N=N'=16
 * DAC-Side JESD204B Lane Rate: 10Gbps
 * ADC-Side JESD204B Lane Rate: 10Gbps
2021-11-19 18:08:16 +02:00
Laszlo Nagy e00def31d0 ad9081_fmca_ebz: versal: Remove external gt_reset logic 2021-11-19 14:01:48 +02:00
Laszlo Nagy 0b9631f1f7 ad9081_fmca_ebz: versal: Rename nets 2021-11-19 14:01:48 +02:00
Laszlo Nagy ca6248ba88 ad9081_fmca_ebz/common/versal_transceiver.tcl: Reset also PLL 2021-11-19 14:01:48 +02:00
Laszlo Nagy 731ed0a7a5 ad9081_fmca_ebz/vck190: Updated to hierarchical versal transceiver
Vivado cannot nest multiple block designs than two layers. This makes
replication of designs difficult.

Create a hierarchy around the Versal transceiver that includes also the
converters, this type of interface would match the util_adxcvr
interface.

Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-11-19 14:01:48 +02:00
Laszlo Nagy 1d951cfbae ad9081_fmca_ebz/vck190: Change default profile to 2 lanes 2021-11-19 14:01:48 +02:00
stefan.raus adad6c930d ad9081_fmca_ebz_qsys.tcl: Add RX_LANE_RATE and TX_LANE_RATE parameters
For ad9081/a10soc project, the RX_LANE_RATE and TX_LANE_RATE were computed
from SAMPLE_RATE. Remove SAMPLE_RATE and add RX_LANE_RATE and TX_LANE_RATE
as parameters. Update also computation examples from comments.

Signed-off-by: stefan.raus <stefan.raus@analog.com>
2021-11-12 13:04:57 +02:00
Robin Getz 63b6711cfa start adding some doc to the ./projects directory
This adds a Readme.md to each project directory with pointers to project
documentation in the wiki, and the drivers (if they exist). This will
help with some autogenerated doc in the wiki, that is generated with the
innovatily named "wiki_summary.sh" shell script that parses through
these Readme.md files, and generates a summary table.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Iacob Liviu Mihai <liviu.iacob@analog.com>
2021-11-10 14:01:06 +02:00
Filip Gherman 9295218a64 projects/ad9081_fmca_ebz: Updated makefiles 2021-10-05 16:56:57 +03:00
Laszlo Nagy 51b643b978 Makefile: Fix misc makefiles from projects and library 2021-10-05 14:24:48 +03:00
Laszlo Nagy 3a1babe366 ad9081_fmca_ebz/vck190: Reset GT with HMC7044 lock
Reset transceiver with a pulse
2021-10-05 14:09:51 +03:00
Laszlo Nagy 2562aead32 ad9081_fmca_ebz/common: Drive Rx DMA system side with DMA clock 2021-10-05 14:09:51 +03:00
Laszlo Nagy 8d547f31e1 ad9081_fmca_ebz/vck190: Initial version 2021-10-05 14:09:51 +03:00
Laszlo Nagy 6c58a8d1ab ad9081_fmca_ebz/common: Add Versal transceiver support 2021-10-05 14:09:51 +03:00
David Winter edd2956d58 data_offload: Fix util_[cu]pack offset to TDD syncs
Signed-off-by: David Winter <david.winter@analog.com>
2021-09-30 14:45:54 +03:00
David Winter b9554a9a5a ad9081_fmca_ebz: Integrate axi_tdd into zcu102 design
Signed-off-by: David Winter <david.winter@analog.com>
2021-09-30 14:45:54 +03:00
Adrian Costina 591a23156b Makefiles: Update header with the appropriate license 2021-09-16 16:50:53 +03:00
David Winter e9e278c898 ad9081_fmca_ebz: Remove bypass gpio
Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
David Winter 2178191610 ad9081_fmca_ebz: Switch util_dacfifo to data_offload engine
Memory requirements are the same as with the dacfifo (1 MiB).

Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
Laszlo Nagy 75b965e87f ad9081_fmca_ebz/zcu102: Enable 204C modes 2021-06-10 09:53:43 +03:00
Laszlo Nagy 27465ce9c0 ad9081_fmca_ebz/zcu102: Fix spaces 2021-06-10 09:53:43 +03:00
Laszlo Nagy 0ad691a603 ad9081_fmca_ebz/zcu102: Differentiate parameters based on lane rate 2021-05-14 15:39:40 +03:00