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84 Commits (890569d53fc08e52a7a084e864b4fd268ba2fffe)

Author SHA1 Message Date
Laszlo Nagy 8183599b51 ad9081_fmca_ebz/zcu102: Fix typo 2021-05-14 15:39:40 +03:00
Laszlo Nagy cf7f45ffcc ad9081_fmca_ebz: Fix for F=8 2021-05-14 15:39:40 +03:00
Laszlo Nagy 7b2ba41bdd ad9081_fmca_ebz/vcu118: Adjust QPLL params and diff swing 
This commit fixes the 16.5Gbps lane rate case where the link drops
after few seconds an initial successful link up happens.
A few seconds delayed calibration process can workaround this but with
having the differential drivers swing increased this is no longer
required.
 2021-05-14 15:39:40 +03:00
Laszlo Nagy 0d9e38bdbe ad9081_fmca_ebz: Update path to common block design 
Use absolute paths so ad9082 wrapper project can include the
system_bd.tcl instead of duplicating code.
 2021-05-14 15:39:40 +03:00
Laszlo Nagy 680d28476c ad9081_fmca_ebz: Add LANE_RATE param to all projects 
The block design expects a lane rate to be set in the system project.
 2021-05-14 15:39:40 +03:00
Laszlo Nagy bd6ec360e2 ad9081_fmca_ebz/vcu118: Set XCVR params for 204C link 
Set XCVR parameter for 204C 24.75 Gbps with a  dynamic range of 10Gbps..24.75Gpbs

Organize XCVR params based on lane rate
 2021-05-14 15:39:40 +03:00
Laszlo Nagy 693c002668 ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd: Add 204C support for XCVR 
Remove Xilinx PHY and simplify project
 2021-05-14 15:39:40 +03:00
Laszlo Nagy d92f925b06 ad9081_fmca_ebz: Disable XBAR from DAC TPL 2021-05-14 15:39:40 +03:00
stefan.raus 4a772265a9 Update Quartus Prime version from 19.3.0 to 20.1.0 
adi_project_intel.tcl: Change quartus version to 20.1.0.
library: Set qsys version so that IP instances won't require a specific version.
 2021-03-08 11:29:33 +02:00
Laszlo Nagy 6b13b32f24 ad9081_fmca_ebz: Workaround DMA bug when bus size equals max burst size 2021-03-04 11:13:29 +02:00
Laszlo Nagy 0374a7c1ac ad9081_fmca_ebz/vcu118: Added common 204C use cases as example 2021-02-05 15:24:15 +02:00
Laszlo Nagy ddd8a14790 ad9081_fmca_ebz: Remove system reset from Xilinx PHY 
Reset in device clock domain caused timing failures.
Since link reconfiguration is not supported the reset is not required.
 2021-02-05 15:24:15 +02:00
Laszlo Nagy af3e1c7003 ad9081_fmca_ebz/a10soc: Np 12 support 2021-02-05 15:24:15 +02:00
Laszlo Nagy bb9eafceef ad9081_fmca_ebz/zcu102: Add case analysis to select correct out clock frequency 2021-02-05 15:24:15 +02:00
Laszlo Nagy d0f8a81b2f ad9081_fmca_ebz: Np 12 support 
204B functional
204C functional
 2021-02-05 15:24:15 +02:00
Laszlo Nagy 0fd5590e56 ad9081_fmca_ebz: a10soc: Initial version 
Parametrizable project with default profile of:

  M=8 L=4 SampleRate=250 MSPS
  LaneRate=10 Gbps
 2021-02-05 10:24:59 +02:00
Sergiu Arpadi 6f2f2b8626 makefile: Regenerate make files 2021-01-20 01:02:56 +02:00
sergiu arpadi acbbd4636a sysid: Upgrade framework, header/ip are now at 2/1.1.a 
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
 2021-01-20 01:02:56 +02:00
Laszlo Nagy da9828a63e ad9081:zcu102: Expose parameters to environment 
Allow setting project parameters from the environment.
 2021-01-19 17:10:08 +02:00
Laszlo Nagy 3dd370a27c ad9081_fmca_ebz: enable xbar in DAC TPL 2020-11-27 09:45:11 +02:00
Laszlo Nagy ad755788a0 ad9081_fmca_ebz/zc706: Initial version 
M=8 L=4 SampleRate=250 MSPS
LaneRate=10 Gbps
 2020-11-12 15:46:27 +02:00
Laszlo Nagy e9f319e3d7 ad9081_fmca_ebz: HP0 is already initialized in ZC706 
On carriers like ZC706 the HP0 interconnect is in already in use so it must
not be initialized here.
 2020-11-12 15:46:27 +02:00
Adrian Costina 9093a8c428 library: Move ad_iobuf to the common library, as it's not Xilinx specific 
Updated all system_project and Makefiles
 2020-11-02 16:13:35 +02:00
Laszlo Nagy 4026eaa19b ad9081_fmca_ebz: Fix device clocks termination 
The device clocks are AC coupled LVDS lines without external termination.
For proper operation internal differential termination must be enabled,
the DQS_BIAS will DC bias the AC coupled signal to VCCO/2 (1.8/2) 0.9V
 2020-10-06 16:13:21 +03:00
Sergiu Arpadi d8ab27b2af sysid: Remove cstring init string 2020-09-30 19:12:24 +03:00
Laszlo Nagy e8f6523197 ad9081_fmca_ebz: adapt to renamed tpl core 2020-05-20 19:08:25 +03:00
Laszlo Nagy cbb23c7b67 ad9081_fmca_ebz: fix Xilinx PHY resets 
Avoid clock domain crossing on resets.
 2020-04-23 17:21:05 +03:00
Laszlo Nagy e112a03d85 ad9081_fmca_ebz: Whitespace cleanup 
Clear extra lines and whitespaces at end of lines.
 2020-04-23 17:21:05 +03:00
Laszlo Nagy 7df4caf8b0 ad9081_fmca_ebz: Added parameter description 
Add parameter description to project and common block design file
 2020-04-23 17:21:05 +03:00
Laszlo Nagy e433d3f808 ad9081_fmca_ebz: expose PLL selection as a parameter 
On the Xilinx PHY the available PLL options depends on the lane rate.
Encoding is:
  0 - CPLL
  1 - QPLL0
  2 - QPLL1

Since the selection of line rate is available from the project also the
PLL selection must be exposed.
 2020-04-23 17:21:05 +03:00
Laszlo Nagy b774e1ca7d ad9081_fmca_ebz: enable IQ rotation 2020-04-03 11:16:37 +03:00
Laszlo Nagy b1f62f09ac ad9081_fmca_ebz:vcu118: initial version 
Use over-writable parameters from the environment.

      e.g.
        make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=12.375 REF_CLK_RATE=375 RX_JESD_L=4 TX_JESD_L=4
        make JESD_MODE=64B66B RX_RATE=16.22016 TX_RATE=16.22016 REF_CLK_RATE=245.76 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4
        make JESD_MODE=8B10B  RX_JESD_L=4 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=8
 2020-03-10 18:19:03 +02:00
Laszlo Nagy f3a7fd8b0d ad9081_fmca_ebz:zcu102: initial version 2020-03-10 18:19:03 +02:00
Laszlo Nagy f3630dd95b ad9081_fmca_ebz: common block design 
Parametrizable block design with selectable JESD physical layer between
Xilinx Phy and ad_utilxcvr.
 2020-03-10 18:19:03 +02:00