Commit Graph

17 Commits (892febe68ad17a9e0178c6eb9c07349c4a49d53d)

Author SHA1 Message Date
AndreiGrozav a7f5746afb ad_dds: Add selectable phase width option. 2018-07-18 18:19:30 +03:00
AndreiGrozav 7b553997ab Add ad_dds.v
It will act as a wrapper for the previous dds modules(phase to angle conv.)
this module will furthermore contain the phase accumulator logic.
2018-07-18 18:19:30 +03:00
AndreiGrozav 35e8454fe7 Rename ad_dds.v to ad_dds_2.v 2018-07-18 18:19:30 +03:00
AndreiGrozav ad7e95b169 ad_dds: Add selectable out data width and fair rounding
The CORDIC has a selectable width range for phase and data of 8-24.
Regarding the width of phase and data, the wider they are the smaller
the precision loss when shifting but with the cost of more FPGA
utilization. The user must decide between precision and utilization.

The DDS_WD parameter is independent of CORDIC(CORDIC_DW) or
Polynomial(16bit), letting the user chose the output width.
Here we encounter two scenarios:
 * DDS_DW < DDS data width - in this case, a fair rounding will be
implemented corresponding to the truncated bits
 * DDS_DW > DDS data width - DDS out data left shift to get the
corresponding concatenation bits.
2018-07-18 18:19:30 +03:00
AndreiGrozav 6a1853654a ad_dds: Separated phase width from data width 2018-07-18 18:19:30 +03:00
AndreiGrozav a96d9bd3c2 ad_dds_sine: Cosmetic updates only 2018-07-18 18:19:30 +03:00
AndreiGrozav 4362c35125 ad_dds: Update for CORDIC algorithm integration
Add parameters:
  - to select the sine generator (polynomial/CORDIC)
  - to select the CORDIC data width(default 16)
Suppress the warnings generated when the DDS is disabled.
2018-07-18 18:19:30 +03:00
Istvan Csomortani 425e803364 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
Istvan Csomortani 84b2ad51e2 license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
Istvan Csomortani 85ebd3ca01 license: Update license terms in hdl source files
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
Rejeesh Kutty 6735333aea common- dac data path split 2016-09-23 16:13:24 -04:00
Adrian Costina 96d363849e ad_dds: Registered dds_scale so that Vivado can optimally map the dsp block 2015-10-09 13:43:14 +03:00
Lars-Peter Clausen 6862655b0d Add .gitattributes file
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
Rejeesh Kutty d4be46cc17 library: register map changes and for mathworks 2014-06-24 14:23:56 -04:00
Rejeesh Kutty 25f416e46f dds output is reset if disabled 2014-03-31 10:01:49 -04:00
Rejeesh Kutty d6256e9e29 library: dds and dcfilter changes, added fifo wrappers 2014-03-10 11:11:16 -04:00