Commit Graph

1718 Commits (896888d495ecdffbe370e8608e4d01ff47a3bc13)

Author SHA1 Message Date
Adrian Costina 896888d495 axi_mc_current_monitor: updated ad7401 driver to send unsigned data 2015-07-02 14:23:19 +03:00
Rejeesh Kutty 18e8914087 fmcjesdadc1/a5gt: pn-errors version 2015-07-01 13:43:12 -04:00
Rejeesh Kutty 35aca98b5f fmcjesdadc1/stap: added 2015-07-01 13:43:10 -04:00
Istvan Csomortani 0102e3e02c fmcomms2_ALL: Preserve backward compatibility for ENABLE/TXNRX control
By default the ENABLE/TXNRX pins are controlled by GPIOs, if the TDD module is enabled, the TDD FSM will take over the control of these two pins.
2015-07-01 13:54:01 +03:00
Istvan Csomortani a497dcabb5 axi_ad9361: Bring up the tdd_enable bit
This line will be the selection bit of the GPIO/TDD_FSM mux for ENABLE/TXNRX control
2015-07-01 13:52:00 +03:00
Lars-Peter Clausen 23034965c8 axi_hdmi_tx_es: Drop strange port initializers
Those were added by mistake. It does not seem to be legal Verilog, but for
some reason Vivado accepts it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 21:16:09 +02:00
Lars-Peter Clausen cb03152f1f axi_hdmi_tx: Don't accidentally send control characters in embedded sync mode
ffff and 0000 are always reserved control characters when using embedded
syncs. So make sure that we never have them in the pixel data, even when
running in full-range mode.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 21:16:09 +02:00
Lars-Peter Clausen cf6052e2a8 axi_hdmi_tx: Add control to bypass chroma sub-sampler
Add a control bit to the register map that allows to bypass the chroma
sub-sampler in the axi_hdmi_tx core. This is primarily interned to be used
to send the test-pattern directly to the HDMI transmitter without modifying
it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 21:16:09 +02:00
Lars-Peter Clausen 9e4fb2d048 imageon: Connect raw data to ILA
Connect the raw HDMI data as generated by the ADV7604 to the ILA. For
debugging it is quite useful to be able to compare the data before and
after conversion pipeline.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:03:03 +02:00
Lars-Peter Clausen e429cb3f5c imageon: Increase ILA buffer size
2048 samples is not even enough for one 1080p line. Increase it to 4096.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:44 +02:00
Lars-Peter Clausen bcd12c8ead imageon: Fix HDMI RX DMA data ILA probe width
The DMA data output of the HDMI RX core is 64-bit wide.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:44 +02:00
Lars-Peter Clausen bc4bb111d9 axi_hdmi_rx: Fix packed 422 mode
Currently the hdmi_de_int signal is asserted one clock cycle too early in
packed 422 mode. As a result the EAV sequence ends up in the first pixel
and every other pixel is off by one.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:44 +02:00
Lars-Peter Clausen 13c122f1a1 axi_hdmi_rx: Add full range support to the TPM
Check for both full range and limited range test-pattern sequences and only
if both don't match assert the tpm_oos signal.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:43 +02:00
Lars-Peter Clausen 4503402eef axi_hdmi_rx: Move TPM to its own module
Move the test pattern matcher to its own module. This makes it easier to
use it in other configurations as well.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:43 +02:00
Lars-Peter Clausen d6c64e031f axi_hdmi_rx: Drop TPG enable from register map
The TPG is no longer part of the RX core and the corresponding bit in the
register map isn't hooked up to anything. So drop it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:43 +02:00
Lars-Peter Clausen 542d64bb5a up_hdmi_rx: Fix enable control
Connect the enable signal in the register map to the up_preset signal so
that it is possible to enable/disable to core at runtime.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:43 +02:00
Lars-Peter Clausen 231a21548c up_hdmi_rx: Fix TPM OOS clear
The TPM OOS status flag is in bit 1. Make sure writing to bit 1 rather than
bit 0 clears the TPM OOS.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:43 +02:00
Rejeesh Kutty 330c205e8e fmcjesdadc1- sys_clk changes 2015-06-30 10:47:21 -04:00
Rejeesh Kutty 185e489802 cpack- signaltap mess 2015-06-29 16:31:53 -04:00
Rejeesh Kutty 6bc24e25eb stap- need to be qsys 2015-06-29 13:26:32 -04:00
Rejeesh Kutty d25e02d7ee stap- need to be qsys 2015-06-29 13:26:20 -04:00
Istvan Csomortani aef6f6b20b imageon: Hdmi_iic_rstn is accessible through a GPIO.
Connect hdmi_iic_rstn to GPIO[33]
2015-06-29 10:48:57 +03:00
Lars-Peter Clausen 6862655b0d Add .gitattributes file
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
Rejeesh Kutty 543e08b67a fmcadc1: sdc updates 2015-06-25 04:25:39 -04:00
Istvan Csomortani c0dd80ccee axi_hdmi_rx: Fix alignment issue on packed formats
Some cases, when software changed the image formats, the packed formats (24bit/pixel) lost alignment.
(the first 32 bit after sof got lost) This commit fix that issue.
2015-06-24 12:43:55 +03:00
Rejeesh Kutty 15740a7d34 fmcjesdadc1- 15.0 updates 2015-06-24 05:31:09 -04:00
Rejeesh Kutty 281a47c117 bsplit- altera version, avalon needs a clock 2015-06-24 05:31:08 -04:00
Rejeesh Kutty f4a1a5817c jesd-align: allow sof pass through -- qsys can only do 1 src-dest 2015-06-24 05:31:06 -04:00
Rejeesh Kutty e1b1e1bc2c ad9250- update to use alt ip interface script 2015-06-24 05:31:04 -04:00
Istvan Csomortani 00bc48bc24 axi_hdmi_rx: Fix synchronization issues 2015-06-24 11:03:39 +03:00
Adrian Costina 4e30a5b0bf axi_ad9250: Updated altera core to work with axi4lite interface 2015-06-23 14:29:23 +03:00
Rejeesh Kutty 714d415804 daq2/a10gx- signaltap changes 2015-06-19 14:33:04 -04:00
Rejeesh Kutty 3e5a5504a7 library/jesd-align- remove signaltap interface 2015-06-19 14:33:03 -04:00
Rejeesh Kutty af2ffbe0a0 library/cpack- add signaltap 2015-06-19 14:33:02 -04:00
Rejeesh Kutty ac6e28c461 library/common: add altera signaltap 2015-06-19 14:33:01 -04:00
Rejeesh Kutty 51e6a74a3d daq2/a10gx- add xmit swap 2015-06-19 14:32:59 -04:00
Rejeesh Kutty d6b1260678 daq2/a10gx- signal tap + gpio 2015-06-19 14:32:58 -04:00
Rejeesh Kutty 8a52631189 libary: util_jesd_align- signal tap interface 2015-06-19 14:32:57 -04:00
Rejeesh Kutty 7e08ff0422 library: added util_jesd_xmit 2015-06-19 14:32:56 -04:00
Rejeesh Kutty 67df6b3ea8 a10gx- disable lab cell on dsp input register 2015-06-19 14:32:54 -04:00
Rejeesh Kutty db76fe3298 tquest- generate the timing report file 2015-06-19 14:32:53 -04:00
Adrian Costina c3ea99d1f8 fmcadc2: Fixed zc706 spi connection 2015-06-19 13:31:59 +03:00
Istvan Csomortani ad743c8403 axi_ad9434: This IP core does not have 'data underflow' port 2015-06-18 16:51:42 +03:00
Adrian Costina 301226c766 fmcjesdadc1: Fixed mdc_mdio connection for kc705 2015-06-18 11:06:47 +03:00
Adrian Costina f01ba54c5f fmcomms1: Fixed mdc_mdio connection for kc705 2015-06-18 11:06:33 +03:00
Adrian Costina 009d33f0a0 ad9467: Fixed mdc_mdio connection for kc705 2015-06-18 11:06:20 +03:00
Adrian Costina 2e46bda916 motcon2_fmc: Update project to use the latest util_gmii_to_rgmii 2015-06-16 17:43:10 +03:00
Adrian Costina d137811952 util_gmii_to_rgmii: Updated core so that it has an option to include a delay controller.
It also allows to configure the fixed delay value so that no additional constraints are needed
The default value of 18 seems to work very well(450mbps tx / 640 mbps rx) on the motor control platform used for tests
2015-06-16 17:39:31 +03:00
Adrian Costina 8fc0e0e62d fmcjesdadc1: Fixed vc707 ethernet connections 2015-06-16 16:27:09 +03:00
Adrian Costina 142f802f54 adv7511: Fixed vc707 ethernet connections 2015-06-16 16:26:58 +03:00