28e8275a5d
library/axi_jesd_gt: split gt lanes
2015-06-12 15:56:03 -04:00
c6ebab7393
library- drp moved to up clock
2015-06-01 13:39:26 -04:00
9762c65868
library- jesd-align port name change
2015-05-20 14:25:21 -04:00
e918588a4b
library: remove axi-min-size parameter
2015-05-19 13:07:48 -04:00
d623f77453
axi_jesd_gt: Added rx_jesd_rst and tx_jesd_rst.
...
Resets for both up clock domain and rx clock domain are needed in some projects
2015-04-30 12:07:36 +03:00
a7a2d194e9
axi_jesd_gt: Switched rx_rst and rx_rst_done to up clock domain, to be compatible with xilinx JESD core
2015-04-28 15:04:18 +03:00
9cdec38532
gt- report device type
2015-02-17 11:43:57 -05:00
fccadcec31
jesd_gt: lpm/dfe programmable
2015-02-13 11:33:25 -05:00
fd305f2eff
es: added kcu105 gth
2014-11-17 09:55:09 -05:00
f8e7796592
axi_jesd_gt: Fix lane number parameters
2014-11-12 17:43:32 +02:00
64ec633438
gt: asymmetric no of lanes
2014-11-11 08:54:24 -05:00
6f723ef9e5
axi_jesd_gt: lane mux on char qualifiers
2014-10-22 15:29:25 -04:00
86724f7fc7
gt: tx lane interleaving
2014-10-15 14:51:00 -04:00
de33722470
up/constr: independent read/write and local constraints
2014-10-02 14:35:59 -04:00
5af2474d51
usdrx1: axi_ad9671 / axi_jesd_gt added signal for frame synchronization
2014-09-23 22:44:33 -04:00
41cc92ef49
Remove BASEADDR/HIGHADDR parameters
...
This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:37 +02:00
cf56a568c6
kcu105: GTH updates
2014-06-05 14:27:38 -04:00
916afd460f
axi_jesd_gt: synchronization support
2014-05-19 14:17:31 -04:00
80e5051894
axi_jesd_gt: initial checkin
2014-04-01 15:14:28 -04:00
Rejeesh Kutty
Adrian Costina
Istvan Csomortani
Lars-Peter Clausen