104e9dfcdc
adc/dac-fifo altera cores
2017-02-28 13:30:50 -05:00
11623e79be
axi_dacfifo: Fix clock for read address generation
2017-02-24 15:47:04 +02:00
3e596347fd
axi_dacfifo: Delete unused wires
2017-02-24 15:45:51 +02:00
ac2e5a9dac
constraints: Update constraints
...
Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
2017-02-24 13:43:32 +02:00
f326c03ff3
axi_dacfifo: Define constraint for bypass
...
The bypass module currently is supported, when the DMA data width
is equal with the DAC data width.
The dac_data output is enabled with dac_valid.
2017-02-24 12:35:42 +02:00
b9d3039568
axi_dacfifo: Register the dac_valid signals
2017-02-24 12:34:58 +02:00
debc6e2066
axi_dacfifo: Data from DMA is validated with dma_ready too
2017-02-24 12:32:25 +02:00
dfcd5214a0
axi_dacfifo: axi_dvalid should come from dacfifo_rd module
2017-02-24 12:28:46 +02:00
1fce57f6c3
axi_dacfifo: Redesign the bypass functionality
2017-02-23 17:32:31 +02:00
573959c826
Makefiles: fixed axi_adxcvr/util_adxcvr Makefiles to include interfaces dependancy
2017-02-23 16:16:34 +02:00
e3ac341aad
axi_dacfifo: Fix constraints
2017-02-21 14:45:18 +02:00
981a61bf16
axi_dacfifo: Clean up the axi_dacfifo_wr.v module
2017-02-17 18:40:02 +02:00
f10866e4c3
axi_*fifo: Delete/replace AXI_BYTE_WIDTH parameter
2017-02-16 19:54:41 +02:00
95a4ea20c8
axi_dacfifo: Delete redundant parameter BYPASS_EN
2017-02-16 19:53:44 +02:00
5fa6dba333
Make: Update Makefiles
2017-02-10 16:32:58 +02:00
1e54b5230f
axi_adxcvr- add m_axi associated clock
2017-02-02 11:17:56 -05:00
806d19febc
axi_adxcvr- add primitive info read
2017-02-01 13:38:29 -05:00
1c9d8c4e7c
axi_adxcvr- add primitive info read
2017-02-01 13:35:02 -05:00
d5af828b9c
Merge branch 'dev' into hdl_2016_r2
2017-01-30 17:10:05 +02:00
a2b2ebbed2
ad_lvds_in- ultrascale/ultrascale+ sim device mess
2017-01-21 20:54:21 -05:00
afcd11da87
adxcvr- add parameters for xcvr config
2017-01-19 12:40:26 -05:00
746b97dd96
xilin/axi_adxcvr: Fix clock and reset nets[C
2017-01-19 15:46:16 +02:00
d3ed417f49
axi_adxcvr: Update the packaging script to fix infer mm issues
...
- Change the clock and reset port name of the AXI slave interface
to s_axi_aclk and s_axi_aresetn. This way we can use the adi_ip_properties
process to infer the interface.
- Define an address space reference to the m_axi interface.
2017-01-19 15:16:04 +02:00
8ebc8fe4e2
updated makefiles
2016-12-09 23:06:41 +02:00
025420d6f8
library/axi_xcvrlb- xcvr changes
2016-11-23 12:00:13 -05:00
8f562fd069
xcvr updates- board procedure
2016-11-22 14:43:36 -05:00
3dbed492b3
util_adxcvr: expose cpll/qpll as it is
2016-11-22 11:32:37 -05:00
3cbe735bd8
util_adxcvr: regenerate from script
2016-11-22 11:21:04 -05:00
c57ffc9364
axi_adxcvr- separate pll reset from channels
2016-11-22 11:12:54 -05:00
b9795c7033
xilinx/util_adxcvr: Update enablement dependencies
2016-11-22 17:33:40 +02:00
9d6c93a5d8
Fix warnings
2016-11-14 15:17:15 +02:00
5731ba3300
fmcomms11- xcvr updates
2016-10-24 09:51:40 -04:00
0beecea02d
util_adxcvr- ultrascale updates
2016-10-19 13:06:10 -04:00
bf949f1a88
axi_xcvrlb- xcvr updates
2016-10-17 16:16:57 -04:00
1b3fcb5863
util_adxcvr- parameter defaults
2016-10-17 16:10:57 -04:00
cc6ca4f0f2
ad_lvds_in- ultrascale sim device
2016-10-10 10:39:47 -04:00
ff980551e6
ad_serdes: SERDES_FACTOR handover missing
...
In modules ad_serdes_in/ad_serdes_out the handover of the parameter
SERDES_FACTOR did not exist, causing unwanted behavioral in case of
factors less than 8.
SERDES_FACTOR must be hand over to DATA_WIDTH parameter of the SERDES
primitive.
2016-10-10 16:38:42 +03:00
39fdf11ef3
util_adxcvr- rx/tx clocks
2016-10-05 13:53:02 -04:00
7ec93ce8e0
util_adxcvr: Fix some typo
...
GTHE4_CHANNEL is instantiated in case of XCVR_TYPE == 2
2016-10-05 17:42:12 +03:00
4f587d2e48
util_adxcvr: Delete trailing whitespaces
2016-10-05 17:41:40 +03:00
48dd4880a3
util_adxcvr- ultrascale+ initial commit
2016-10-03 16:11:45 -04:00
0e8551545c
util_adxcvr- ultrascale+ initial commit
2016-10-03 16:11:45 -04:00
b4652650e4
util_adxcvr- xcvr_type parameter
2016-10-03 16:11:45 -04:00
63ddcf1e26
util_adxcvr- synthesis warnings fix
2016-10-03 16:11:45 -04:00
6b956066ef
xilinx/ad_lvds*- ultrascale+
2016-09-30 11:55:10 -04:00
9defccef70
dacfifo- axi address map fixes
2016-09-27 14:48:23 -04:00
21b5e9c634
hdlmake- updates
2016-09-21 11:56:03 -04:00
0def596b43
axi_xcvrlb- updates
2016-09-21 11:04:22 -04:00
d497a7b0ae
axi_xcvrlb- constraints
2016-09-21 11:04:22 -04:00
1860d72df6
axi_xcvrlb- updates
2016-09-19 12:39:59 -04:00
5592c2780e
axi_xcvrlb- loopback version
2016-09-19 12:39:59 -04:00
38f1521861
xilinx/ad_serdes_in : Fix some typos
2016-09-19 16:02:52 +03:00
ff0f659a33
xilinx/ad_serdes_clk : Rename parameter MMCM_DEVICE_TYPE to DEVICE_TYPE
2016-09-19 16:02:06 +03:00
6510f92c12
ad_serdes : Cosmetic changes
2016-09-16 14:45:39 +03:00
a2d15acb89
ad_serdes- altera/xilinx sync
2016-09-15 13:33:55 -04:00
3b0c1e02fc
axi_dacfifo: Move IP to library/xilinx
2016-09-15 11:38:16 +03:00
3cbbc771a8
axi_adcfifo: Move IP to library/xilinx
2016-09-15 11:36:47 +03:00
10b9a0e52f
upadated xcvr ips
2016-08-17 15:51:55 -04:00
3427965cd2
adxcvr- add u-gth bufg
2016-08-11 10:00:41 -04:00
829e4155ca
modified transceiver configuration files
2016-08-10 14:59:38 -04:00
1d33d7d7ee
lib_refactoring: Move the CMOS interface modules to ~/library/xilinx/common
2016-08-08 15:07:42 +03:00
b806fa3b42
lib_refactoring: Move all the Xilinx common modules to library/xilinx/common
2016-08-08 15:06:10 +03:00
5faf4c4976
cleanup: Don't need Makefiles specific to xilinx/altera libraries. Top Makefile covers them
2016-08-05 16:27:52 +03:00
d60bce654c
Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
2016-08-05 15:16:04 +03:00
cb23ba8bb7
make- script needs update
2016-08-04 14:17:04 -04:00
e42b4ea378
hdlmake- updates
2016-08-04 13:28:25 -04:00
2b7c976be5
xcvr- altera/xilinx split
2016-08-04 13:26:10 -04:00
Rejeesh Kutty
Istvan Csomortani
Adrian Costina
AndreiGrozav
Shrutika Redkar