Make sure that the right hand side expression of assignments is not wider
than the target signal. This avoids warnings about implicit truncations.
None of these changes affect the behaviour, just fixes some warnings about
implicit signal truncation.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.
New license looks as follows:
Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.
Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
(at the option of the user):
1. The GNU General Public License version 2 as published by the
Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
OR
2. An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
Add a room output on the input side that reports how many free entries the
FIFO has and a level output on the output side that reports how many valid
entries are in the FIFO.
Note that the level output is only accurate if the output of the FIFO is not
registered, otherwise it might be off by one.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Bring back the AXIS FIFO as a separate module instead of embedding it into
the DMAC module. This makes it possible to use it in other modules outside
of the DMAC.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Istvan Csomortani
Lars-Peter Clausen