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85 Commits (8ad8ec4d1e4f19730e7e3302667457e7f937784c)

Author SHA1 Message Date
Rejeesh Kutty 73680d1ed9 fmcomms2/ml605: removed 2015-03-12 11:59:18 -04:00
Rejeesh Kutty 1cf8092ba9 fmcomms2/zc706: spi/gpio changes 2015-03-10 16:06:22 -04:00
Rejeesh Kutty 631c71373a fmcomms2/zc706: spi/gpio changes 2015-03-10 16:06:18 -04:00
Rejeesh Kutty 796a0f4f2b fmcomms2/zc706: spi/gpio changes 2015-03-10 16:06:13 -04:00
Rejeesh Kutty 7012172f66 fmcomms2: spi/gpio moved to base design 2015-03-10 15:27:32 -04:00
Rejeesh Kutty 7da65ef3db fmcomms2: spi/gpio moved to base design 2015-03-10 15:27:28 -04:00
Rejeesh Kutty abae36b12f fmcomms2: spi/gpio moved to base design 2015-03-10 15:27:22 -04:00
Rejeesh Kutty 9e57e919c4 fmcomms2: spi/gpio moved to base design 2015-03-10 15:26:57 -04:00
Rejeesh Kutty 288f5378ff rfsom: schematic changes 2015-02-18 14:32:41 -05:00
Rejeesh Kutty 93e2bcd911 rfsom: schematic changes 2015-02-18 14:32:30 -05:00
Rejeesh Kutty 996e1b7970 rfsom: constraint updates 2015-02-03 14:20:34 -05:00
Adrian Costina 47871287f3 kc705: Updated base project with linear flash. Updated all depending projects 2015-01-13 10:19:07 +02:00
Rejeesh Kutty b9e2c5659f fmcomms2: 2014.4 2015-01-09 14:12:54 -05:00
Rejeesh Kutty d2baf17ff0 rfsom: updated to rfsom 2014-12-23 14:04:02 -05:00
Rejeesh Kutty 3d1ba585ee rfsom: updated to rfsom 2014-12-23 14:04:01 -05:00
Rejeesh Kutty 19c2da836c rfsom: updated to rfsom 2014-12-23 14:03:59 -05:00
Rejeesh Kutty 4b571ded8f fmcomms2/rfsom: initial commit 2014-12-23 14:03:56 -05:00
Rejeesh Kutty 8e41af7b92 fmcomms2: 2014.4 update 2014-12-23 14:03:54 -05:00
Adrian Costina 2ff72d60d1 fmcomms2: Updated VC707 project to fix ethernet problem 2014-12-19 15:45:05 +02:00
Adrian Costina 86ad9213e0 fmcomms2: Update c5soc system_timing script 2014-12-10 17:54:11 +02:00
Rejeesh Kutty 4cf435ee39 fmcomms2/ml605: compilation fixes 2014-12-09 14:32:39 -05:00
Rejeesh Kutty 8b41034825 fmcomms2/ml605: compilation fixes 2014-12-09 14:32:39 -05:00
Adrian Costina 7a55db59f6 fmcomms2: Zed, fixed iic multiplexer ad_iobuf connections 2014-11-28 14:19:08 +02:00
Adrian Costina 303a2683a2 fmcomms2: Added iic_fmc_intr to the zed top file 2014-11-26 11:26:58 +02:00
Adrian Costina 6227bc82c0 fmcomms2: Updated vc707 project 
- updated constraints
- updated interrupts
- used ad_iobuf
- added linear_flash
 2014-11-26 11:25:19 +02:00
Adrian Costina 2f77daf71d fmcomms2: Updated mitx045 project. Updated constraints. Updated interrupts 2014-11-26 11:21:20 +02:00
Adrian Costina ad08c62b36 fmcomms2: Updated zc702 project. Updated interrupts. Updated constraints 2014-11-07 14:01:55 +02:00
Adrian Costina 4e11e39956 fmcomms2: Updated zed project 
- Updated interrupt system to the latest implementation
- Fixed constraints
 2014-11-07 13:59:46 +02:00
Adrian Costina 962df53946 fmcomms2: Updated kc705 project to vivado 2014.2. 
- Updated interrupt system to the latest implementation
- Fixed constraints
- Used ad_iobuf
 2014-11-07 13:58:40 +02:00
Adrian Costina db18ed4af2 fmcomms2: Updated ac701 project to vivado 2014.2. 
- Updated interrupt system to the latest implementation
- Fixed constraints
- Used ad_iobuf
 2014-11-07 13:56:00 +02:00
Adrian Costina 7e2a9ce569 fmcomms2: Updated base design interrupt system for microblaze 2014-11-07 13:54:43 +02:00
Adrian Costina 6fac294b6f fmcomms2: Updated zc706 project to new interrupt system 2014-10-31 14:15:29 +02:00
Adrian Costina d04a545a41 fmcomms2: updated zc706 project with new constraint style 2014-10-27 19:27:36 +02:00
Istvan Csomortani 17675863e0 all_projects: Fix the interrupt connections to preserve IRQ layout 2014-10-22 11:48:08 +03:00
Istvan Csomortani 4b8720b551 fmcomms2_zc706: Remove top level constraints 
Remove all the unnecessary top level constraint definitions.
 2014-10-20 13:25:01 +03:00
Istvan Csomortani f528873fa9 fmcomms2: Add an additional SPI interface for up/down converter board 
Supported carriers are: ZC706, ZC702 and Zed.
 2014-10-10 18:47:07 +03:00
Istvan Csomortani ca4c961891 fmcomms2: Use ad_iobuf instance on system_top 
Use ad_iobuf instance on system top, instead of separate IOBUF instances.
 2014-10-10 18:45:39 +03:00
Istvan Csomortani e21d26e456 fmcomms2: Cosmetic changes 
Get rid of unwanted whitespaces.
 2014-10-10 18:25:17 +03:00
Istvan Csomortani fe8a076b2e fmcomms2: Cosmetic changes on *_bd.tcl script 2014-10-10 17:06:32 +03:00
Lars-Peter Clausen 7a9e694446 fmcomms2: Connect DMA directly to the HP ports 
The DMA controller is able to send AXI3 compatible requests, no need to add
a interconnect for protocol conversion in between the DMA controller and the
HP port.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-10-10 16:25:14 +03:00
Lars-Peter Clausen 87047fd83e fmcomms2: Set dac_unpack channels to 4 
There are only 4 DAC channels in the fmcomms2 design, so set the number of
channels of the dac_unpack core to 4. This slightly reduces resource usage
as well as reducing the DMA alignment requirement from 128bit to 64bit.  The
later value is what existing applications expect the alignement requirement
to be.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-10-10 16:25:06 +03:00
Istvan Csomortani 2da395926e fmcomms2: Upgrade project to 2014.2 2014-10-09 18:54:33 +03:00
Adrian Costina 7e40f99fe9 fmcomms2: Improved constraints for ac701 and zc702. Fixed common design so that ILA works correctly on microblaze based systems 2014-09-23 22:28:27 -04:00
Adrian Costina f43b5d707e fmcomms2: Reduced clock frequency for ILA to meet timing for ZED 
Modified ZED constraints to 250 MHz for the clock from AD9361
 2014-09-16 16:08:28 -04:00
Lars-Peter Clausen d8651cdd2e fmcomms2: c5soc: Set dac_util_unpack number of channels to 4 
We only do have 4 channels in this design. Reducing the number of supported
channels for the dac_util_unpack core to 4 from 8 lowers the DMA alignment
requirement from 128bit to 64bit.  We need this since applications only
expect a DMA alignment requirement of 64bit.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-09-12 16:15:12 +02:00
Lars-Peter Clausen ecc498313c fmcomms2: c5soc: Connect ADC, DAC and VGA DMA to different bridge interconnects 
We have enough bridge interconnect to give each DMA its own, so use them.
This makes sure that they do not interfere with each others transfers to
much. The SDRAM controller side of the FPGA2SDRAM bridges FIFO runs at a
much faster frequency then what we are able to use in the fabric. So its
better to do the arbitration on that side of the bus to make sure that we
can utilize the buses in the FPGA fabric to the maximum for each DMA core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-09-12 16:14:07 +02:00
Adrian Costina 61f21a17b3 fmcomms2:c5soc project upgraded with util_dac_unpack 2014-09-11 15:13:09 -04:00
Lars-Peter Clausen 4c1c50788e fmcomms5: c5soc: Fix typo 
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-09-11 17:15:10 +02:00
Lars-Peter Clausen c7989925c5 fmcomms2: c5soc: Add false path between 50MHz and VGA PLL clock 
Otherwise we get timing errors for the reset signal that is generated in the
50MHz clock domain, but used in the VGA PLL clock domain.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-09-09 15:05:06 +02:00
Lars-Peter Clausen 328205c31d fmcomms2: c5soc: Set DMA transfer length to 24 bits 
14 bits is a bit to low and we use 24 bits everywhere else as well.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-09-09 15:05:06 +02:00