4 Commits (8ba86cb75c961c69a52d92e9df02a1c818bba14e)

Author	SHA1	Message	Date
Adrian Costina	be6fa287fa	axi_dac_interpolate: Make dac_reset external	2017-04-18 12:17:39 +02:00
Istvan Csomortani	c1bdfca4c3	library: Delete all adi_ip_constraint process call	2017-04-06 12:36:47 +03:00
Istvan Csomortani	ac2e5a9dac	constraints: Update constraints ... Xilinx recommends that all synchronizer flip-flops have their ASYNC_REG property set to true in order to preserve the synchronizer cells through any logic optimization during synthesis and implementation.	2017-02-24 13:43:32 +02:00
Adrian Costina	9c975211da	axi_dac_interpolate: Initial commit	2017-01-31 16:22:49 +02:00