8c0782cb74
ad9625x2_fmc: constraints changes
2014-11-03 15:01:40 -05:00
beee377fb7
ad9625x2_fmc: interrupts fix
2014-11-03 15:01:15 -05:00
8e6cb2bad4
ad9625x2_fmc: dma fifo additions
2014-11-03 15:00:51 -05:00
7ad9340992
pmod_ad7175: Connect gain control pin
...
Connect the gain control pin to GPIO32 of the ZYNQ.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-11-03 15:00:02 +01:00
4eea04cc9d
fmcadc3: zc706: Fix DMA enable connection
...
Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
2014-11-03 14:45:16 +01:00
57137df018
fmcjesdadc1_zc706: Interrupt update
2014-11-03 13:02:09 +02:00
4f815b99a1
kc705_base: Fix sys_concat_intc input connections
...
All the unused input pins need to be connected to ground.
2014-11-03 13:02:08 +02:00
8ef3eada7d
adv7511_ac701: Interrupt update
2014-11-03 13:02:07 +02:00
98b92c4bc1
adv7511_kc705: Interrupt update
2014-11-03 13:02:06 +02:00
0246a40e28
adv7511_vc707: Interrupt update
2014-11-03 13:02:05 +02:00
f7588131da
ac701_base: Interrupt update
2014-11-03 13:02:04 +02:00
b92636c6eb
kc705_base: Interrupt update
2014-11-03 13:02:03 +02:00
25f37ffce7
usdrx1: Added cpld configuration files
2014-11-03 12:54:54 +02:00
99ad286c41
kcu105: adv7511 updates
2014-10-31 13:28:17 -04:00
8ed9d10502
ad9625_fmc: disable sync
2014-10-31 13:05:18 -04:00
6f5a268909
fmcomms1: ZC706, updated project with latest constraints and interrupts
2014-10-31 17:59:56 +02:00
a84397d345
motor_control: Changed the encoder pins mapping.
2014-10-31 17:37:28 +02:00
356e1c7ac1
motor_control: Changed the encoder pins mapping.
2014-10-31 17:08:18 +02:00
3c78d8fe58
ad9265_fmc: Added correct fifo to ILA. Updated interrupts
2014-10-31 14:49:29 +02:00
6fac294b6f
fmcomms2: Updated zc706 project to new interrupt system
2014-10-31 14:15:29 +02:00
91ea11041d
prcfg_mitx045: Upgrade of the project script.
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- the design using the common PN monitor
- the first implemented logic will be the qpsk, to get a better result
- cosmetic changes
2014-10-31 12:18:00 +02:00
e450e78f13
prcfg: Update design to Vivado 2014.2
2014-10-31 12:05:19 +02:00
860a7caa56
prcfg: dac and adc to dma interface width is 64
2014-10-31 12:04:34 +02:00
ea194755e1
prcfg: Upgrade the QPSK logic
...
Regenerate the qpsk logic, with the new HDL coder, and modify the design to support the new files.
2014-10-31 11:59:29 +02:00
16cdae3001
mitx045_base: Delete unnecessary timing constraints.
2014-10-31 11:50:49 +02:00
07673b673a
adv7511_mitx045: Interrupt update
2014-10-31 11:46:27 +02:00
67bec719f7
mitx045_base: Interrupt update
2014-10-31 11:45:33 +02:00
b9f800ff65
fmcadc3: zc706: Fix connection to the system clock
...
Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
2014-10-31 11:06:16 +01:00
21f99b1c97
daq2: remove ila for kcu105
2014-10-30 15:26:29 -04:00
56859ad4c9
sys_dmafifo: use internal memory
2014-10-30 15:26:28 -04:00
5bd00df33a
adv7511_zc706: Interrupt update
2014-10-30 19:02:16 +02:00
d81484a6f3
adv7511_zed: Interrupt update
2014-10-30 19:01:17 +02:00
7ae003cf82
zed_base: Interrupt update
2014-10-30 19:00:05 +02:00
e0b7ef2f4f
scripts: Update scripts for PR design flow
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+ Rewrite the pr_verify process, to improve verification time
+ Update the implementation flow: always the biggest logic will be implemented first, to achieve a better result
therefore force the tool to optimize the first logic with 'ExploreSequentialArea'
+ Make utilization report just from the PR pblock, that's more relevant as the utilization report of the whole fabric
2014-10-30 18:51:13 +02:00
02b32abefe
adv7511_zc702: Interrupt update
2014-10-30 18:42:14 +02:00
ba53e156e3
ZC702_base: Interrupt update
2014-10-30 18:39:49 +02:00
f595b86576
kcu105: lutram constraints for ies
2014-10-30 11:20:27 -04:00
d0a70380bf
kcu105: lutram constraints for ies
2014-10-30 11:19:55 -04:00
4c0e4d280f
dmafifo: internal version- light duty
2014-10-30 11:12:13 -04:00
360e7104b6
dmafifo: axi version- heavy duty
2014-10-30 11:12:12 -04:00
cfa1a93441
Merge branch 'dev' of https://github.com/analogdevicesinc/hdl into dev
2014-10-30 08:42:09 +01:00
56374cf592
usdrx1: Added synchronization, updated constraints, added timing check for a5gt project
2014-10-29 19:29:42 +02:00
cc265b6b9c
daq2/daq3/ad9625_fmc: Connect ADC DMA xfer_req signal
...
For proper operation the xfer_req signal needs to be connected from the ADC DMA to the DDR FIFO.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-29 18:15:54 +01:00
8c789104a6
ad9671: Fixed constraints. Modified system_timing.tcl so that it will fail if timing are not met
2014-10-29 18:25:56 +02:00
2e01ad2eec
ad9625_fmc/zc706: ps7 interrupt updates
2014-10-29 12:13:44 -04:00
b7946febfa
Merge branch 'dev' of https://github.com/analogdevicesinc/hdl into dev
2014-10-29 08:50:51 +01:00
f83622a2e6
daq2/kcu105: interrupt updates
2014-10-28 15:51:42 -04:00
4788d09620
vc707: interrupt updates
2014-10-28 15:42:55 -04:00
c9691fac64
ad9625_fmc: merge zc706 and vc707
2014-10-28 10:12:19 -04:00
627da6161b
ad9625_fmc: remove dma clock for now - zynq/non-zynq merge
2014-10-28 10:12:18 -04:00
Rejeesh Kutty
Lars-Peter Clausen
Paul Cercueil
Istvan Csomortani
Adrian Costina
acozma
Michael Hennerich