b0eff57b0f
fmcomms2/zc702: Fix critical warnings
2016-12-08 19:54:52 +02:00
170c781d02
hdlmake.pl- updates
2016-12-01 13:52:11 -05:00
69ee410d3d
fmcomms2/zc706pr- bypass pr as default
2016-11-21 09:45:10 -05:00
1cbea90bac
altera - a10gx bank swap
2016-11-01 12:41:25 -04:00
1e0fed82f7
alt_serdes- a10 ddio fixes
2016-11-01 12:41:25 -04:00
671a547c2b
hdlmake- updates
2016-11-01 12:41:25 -04:00
7b958fed87
hdlmake- updates
2016-10-21 13:59:43 -04:00
17cfdd6be9
fmcomms2/a10gx: Update Makefile and qsys script
2016-10-18 12:42:14 +03:00
cb97bc500a
hdlmake updates
2016-10-17 16:29:57 -04:00
905e29eb01
hdlmake- altera
2016-10-10 12:55:55 -04:00
8e1034946f
fmcomms2/zcu102- 2016.2 updates
2016-09-30 11:55:10 -04:00
f1e787f86b
fmcomms2: TDD control is enabled by default
2016-09-16 14:45:39 +03:00
16ee1336c3
Makefile: Update make files
2016-09-15 11:41:06 +03:00
f697490de6
hdlmake- updates
2016-08-19 15:59:41 -04:00
0b0aa8e6c0
Makefile: Add MMU option to altera makefiles
2016-08-11 17:46:54 +03:00
0cd608a7e2
lib_refactoring: Update Make files
2016-08-08 16:38:38 +03:00
df36902713
lib_refactoring: Fix path of the IO macros
2016-08-08 15:07:19 +03:00
d60bce654c
Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
2016-08-05 15:16:04 +03:00
e42b4ea378
hdlmake- updates
2016-08-04 13:28:25 -04:00
7ca8e10004
make: Update Make files
2016-08-01 14:24:48 +03:00
af4c43b6e1
hdl-vivado-2016.2: Update fmcomms2 and pzsdr base design
2016-08-01 13:49:12 +03:00
39a5534e00
hdlmake- updates
2016-07-21 16:10:38 -04:00
12abe2b6b9
fmcomms2: Makefile update
2016-07-12 09:39:24 +03:00
283bf9ad75
fmcomms2_a10GX: Add fmcomms2 on a10gx
2016-07-11 18:37:18 +03:00
e9fe752b7a
fmcomms2_qsys.tcl: Add fmcomms2 block design script for Altera
2016-07-11 18:34:21 +03:00
48762519b5
make updates
2016-07-06 15:02:00 -04:00
67c948e821
fmcomms2/a10soc-- bad board design
2016-06-14 12:29:36 -04:00
eaf4d4a19d
makefile updates
2016-06-10 14:26:14 -04:00
09520709b0
make updates
2016-05-20 12:35:45 -04:00
e1350018da
zcu102- updates
2016-05-10 15:40:41 -04:00
a6411dbd63
zcu102- added
2016-05-10 15:40:41 -04:00
8d72b645ae
fmcomms2/common: Remove ila_tdd block
2016-05-09 10:28:10 +03:00
ddfaff2cf5
fmcomms2/a10soc: compile version
2016-05-04 13:42:12 -04:00
f4e5965936
fmcomms2/a10soc: ip updates
2016-05-04 13:42:12 -04:00
385ed31a45
make files update
2016-04-29 10:17:35 -04:00
61b531b1c1
a10soc device update
2016-04-29 10:17:35 -04:00
e790e4c3ae
a10soc- complete qsys
2016-04-25 12:56:19 -04:00
bfa6fe2a40
a10soc- updates
2016-04-25 11:23:16 -04:00
28159aeec9
a10soc- updates
2016-04-25 11:11:46 -04:00
0a3967b886
a10soc- updates
2016-04-25 10:53:26 -04:00
d36d1263c5
a10soc- updates
2016-04-25 10:50:09 -04:00
2a5f31d26b
fmcomms2/a10soc- copy
2016-04-22 15:15:44 -04:00
679d471d75
Merge branch 'hdl_2016_r1' into dev
...
hdl_2016_r1 contains IP core upgrades to Vivado 2015.4.2 and hdmi_tx improvements.
2016-04-19 18:05:50 +03:00
3006c5a223
make updates
2016-04-11 16:14:59 -04:00
21208ca208
Makefiles: Update Makefiles
2016-03-31 12:37:47 +03:00
995debedce
fmcomms2: Update common design to 2015.4
2016-03-18 15:26:52 +02:00
ceea7f25b2
fmcomms2: Updated common design to 2015.4
2016-03-15 15:23:20 +02:00
e381d5170c
util_tdd_sync: Update the synchronization interface
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Simplify the synchronization interface, there is one signal line between the synchronization module and transceiver core.
2016-02-12 14:27:37 +02:00
c051a578e5
fmcomms2: Delete unnecessary clock definition
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The two clocks, rx_clk and ad9361_clk, are the same.
2015-11-20 19:35:37 +02:00
2345d29663
fmcomms2: Update make files
2015-11-11 11:15:45 +02:00
a936ad607f
fmcomms2/zc706: Delete unused files from file list
2015-11-11 11:14:58 +02:00
c7e86528d6
fmcomms2/zc706: Cosmetic changes on constraints file
2015-11-11 11:14:16 +02:00
6197a82c80
fmcomms2/common: Add the util_tdd_sync module
2015-11-11 11:07:15 +02:00
9d2b8809df
Makefiles: Updated Makefiles
2015-10-23 10:44:27 +03:00
21737ad7b8
fmcomms2/zc706pr: Update the fifo interface of the PR module
2015-10-13 11:37:44 +03:00
c9a5057b93
library/prcfg : Split data bus to channels
...
Because of the new pack/upack modules on the data path, it makes more sense to split the data interface of the PR modules into separate channels.
The top module will supports max 4 channels.
2015-10-13 11:36:45 +03:00
c83239b014
fmcomms2/zc706pr: Update PR design
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+ Add system_top.v to design
+ Add pr specific constraints
2015-10-09 13:23:42 +03:00
f77f928444
fmcomms2/zed: Fix the system_top
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Fix the enable/txnrx control line.
2015-09-25 19:11:41 +03:00
aeb1d7aa3e
fmcomms2/zed: Cosmetic changes
2015-09-25 19:11:39 +03:00
f8b3096bd0
fmcomms2/vc707: Fix the system_top
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Fix the enable/txnrx control lines.
2015-09-25 19:11:37 +03:00
2c75cfd04e
fmcomms2/vc707: Cosmetic changes
2015-09-25 19:11:35 +03:00
ffa0bcd19f
fmcomms2/mitx045: Fix the system_top
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Fix the enable/txnrx control lines.
2015-09-25 19:11:32 +03:00
28d20e84c5
fmcomms2/zc702: Fix the system_top
...
Fix the enable/txnrx control lines.
2015-09-25 19:11:30 +03:00
ea74413125
fmcomms2/kc705: Fix the system_top.
...
Fix the enable/txnrx control lines.
2015-09-25 19:11:28 +03:00
f80622b972
fmcomms2/ac701: Fix the system_top
...
Fix the enable/txnrx control line.
2015-09-25 19:11:26 +03:00
cd8b467b1e
fmcomms2: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:07 +02:00
a679251d7d
Makefiles: Update Make
2015-09-09 17:13:19 +03:00
510f1cfdd9
fmcomms2_zc706: Update project with the new TDD sync interface
2015-09-09 12:35:22 +03:00
a92e049e8f
fmcomms2_bd- another attempt at ila width
2015-08-27 13:17:08 -04:00
b8f9b7040d
fmcomms2- tdd ila fixes
2015-08-27 11:55:41 -04:00
026fad8853
fmcomm2- enable/txnrx- through devif
2015-08-27 11:41:58 -04:00
6a9790484f
fmcomm2- enable/txnrx- through devif
2015-08-27 11:41:56 -04:00
2e1e0939ce
fmcomms2- dma parameters & ila cores upgrade
2015-08-26 14:12:57 -04:00
9e5e7d6805
remove rfsom from fmcomms2
2015-08-20 10:33:43 -04:00
d52308f074
axi_dmac: Change parameter name 2D_TRANSFER
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Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 10:14:22 +03:00
57cfb7cfb1
hdl/library: Update the IP parameters
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The following IP parameters were renamed:
PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
2015-08-19 14:11:47 +03:00
10d9de39a1
axi_ad9361/tdd: Update the synchronization logic
...
The master will regenerate a sync pulse periodically. The period can be defined by software.
2015-08-19 12:21:23 +03:00
bcee3e04d4
fmcomms2_tdd: Update tdd_enabaled path
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This line controls the mux, which switch between hdl and software (GPIO) control of the ENABLE/TXNRX pins.
Fix the broken path and change the name from "tdd_enable" to "tdd_enabled".
2015-08-19 12:14:05 +03:00
d2c99acae8
fmcomms2/TDD: Update synchronization interface
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Synchronization is done by a simple req/ack interface between a master and slave terminal.
2015-08-06 15:14:36 +03:00
8e631e56d6
fmcomms2: Add a synchronization interface for TDD mode.
...
Supported carrier are ZC706 and RFSOM.
The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled.
By default a terminal is slave, software must write 0x01 into TDD register 0x50.
2015-07-28 14:42:54 +03:00
28aea82952
fmcomms2_zc702: Add SPI and GPIO interface for FREQCVT
2015-07-22 10:16:04 +03:00
a7da779b94
Makefile: Updated Makefiles
2015-07-16 18:19:42 +03:00
1dcbf5e5a2
fmcomms2/zc706: Fix GPIO connections
...
Fix GPIO connections for the FREQCVT board.
2015-07-15 15:12:01 +03:00
a38339a3ec
fmcomms2/rfsom: Add GPIO control for the RF card
2015-07-14 13:12:54 +03:00
ba2029a6e8
fmcomms2/rfsom: Delete trailing whitespaces from system_constr.xdc
2015-07-14 13:12:53 +03:00
46fa91d5be
Makefile: Update Make files
2015-07-03 18:08:57 +03:00
95500d4022
fmcomms2_rfsom: Fix GPIO connections
2015-07-03 13:03:19 +03:00
0102e3e02c
fmcomms2_ALL: Preserve backward compatibility for ENABLE/TXNRX control
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By default the ENABLE/TXNRX pins are controlled by GPIOs, if the TDD module is enabled, the TDD FSM will take over the control of these two pins.
2015-07-01 13:54:01 +03:00
6862655b0d
Add .gitattributes file
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Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
25e56a4d03
arradio: renamed fmcomms2 c5soc to arradio
2015-06-08 11:35:21 +03:00
dc7064ab95
fmcomms2/vc707 - wfifo changes
2015-06-05 12:44:04 -04:00
25f1ad73f0
fmcomms2/freqcvt: Update SPI interface I/O
2015-06-05 18:16:14 +03:00
f1e75963a2
fmcomms2: wfifo+pack changes
2015-06-05 09:20:50 -04:00
3b1ea7e528
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch
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598ece4c8d
2015-06-04 18:09:47 +03:00
f81d22a17a
altera- common timing check
2015-06-04 10:56:32 -04:00
a6cae6b477
iobuf: do is a system verilog keyword
2015-05-21 14:06:17 -04:00
6b9906b22b
Refresh Makefiles
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Re-generate the Makefiles after a small update to the generation script:
- Entries are sorted alphabetically
- Empty dependency lines are skipped
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 14:21:54 +02:00
0805da3b6b
fmcomms2/rfsom- enable dac delay
2015-05-18 16:45:54 -04:00
3e51d29f75
enable/txnrx- tdd changes
2015-05-18 14:28:20 -04:00
c19749361d
Makefiles: Updated makefiles to have as a result the programming file instead of the project file.
...
Also fixed altera projects dependencies
2015-05-18 17:22:46 +03:00
AndreiGrozav
Rejeesh Kutty
Istvan Csomortani
Adrian Costina
Lars-Peter Clausen