Dan Hotoleanu
f34b561e19
daq3: Parameterize JESD204 configuration values
...
Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line for the Xilinx FPGAs in the project.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2022-01-31 10:47:01 +02:00
LIacob106
58c1d2e3b2
projects: fixed xcvr clocks that generated critical warning
2021-11-09 12:40:14 +02:00
LIacob106
d4126739b4
projects: remove hardcoded div_clk from xcvr
2021-10-27 12:11:22 +03:00
Adrian Costina
591a23156b
Makefiles: Update header with the appropriate license
2021-09-16 16:50:53 +03:00
Sergiu Arpadi
6f2f2b8626
makefile: Regenerate make files
2021-01-20 01:02:56 +02:00
sergiu arpadi
acbbd4636a
sysid: Upgrade framework, header/ip are now at 2/1.1.a
...
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
2021-01-20 01:02:56 +02:00
Adrian Costina
9093a8c428
library: Move ad_iobuf to the common library, as it's not Xilinx specific
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Updated all system_project and Makefiles
2020-11-02 16:13:35 +02:00
Sergiu Arpadi
d8ab27b2af
sysid: Remove cstring init string
2020-09-30 19:12:24 +03:00
Istvan Csomortani
aa5fdf903e
Makefile: Update makefiles
2019-08-26 16:58:01 +03:00
Arpadi
0680e44330
system_id: deployed ip
2019-08-06 16:53:11 +03:00
Istvan Csomortani
a589753d92
project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl
2019-06-29 06:53:51 +03:00
Istvan Csomortani
43725429ac
adi_project: Rename the process adi_project_xilinx to adi_project
2019-06-29 06:53:51 +03:00
Istvan Csomortani
f22f448d4b
daq3:vcu118: Delete constraint related to smart connect
...
Apparently this constraint will cause more harm than good. The tool will
try to prevent an invalid hold violation by increasing the net delay,
causing a setup violation on the same path. (inside the smart connect)
See more info here:
https://forums.xilinx.com/t5/AXI-Infrastructure/Smartconnect-and-Synchronous-Clock-Domain-Crossing-Issues/td-p/904824
2019-06-27 13:47:24 +03:00
Adrian Costina
f5ed5def27
daq3: vcu118 initial commit
2019-04-17 14:24:35 +03:00