cfe0c0ced5
adi_project_xilinx.tcl, adi_ip_xilinx.tcl: update version to 2021.1
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Update vivado version from 2020.2 to 2021.1 in projects and library scripts.
2021-09-24 12:11:11 +03:00
1fe0d5f8e0
data_offload: Fix timing violation
2021-09-22 12:18:33 +03:00
cdb9a0af2b
data_offload: Add sync to cyclic mode
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Signed-off-by: David Winter <david.winter@analog.com>
2021-09-21 09:06:03 +03:00
76cd5581bc
axi_pwm_gen: Add config in soft reset option
2021-09-17 11:50:46 +03:00
591a23156b
Makefiles: Update header with the appropriate license
2021-09-16 16:50:53 +03:00
b38747cefc
Make system: Be explicit in license that cover the make/build system
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The build system is covered under a 1 Clause BSD license. Make sure
users are aware.
Signed-off-by: Robin Getz <robin.getz@analog.com>
2021-09-16 16:50:53 +03:00
12a3f8799e
JESD204 Interface Framework : add logo
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Add a small logo for branding purposes.
Signed-off-by: Robin Getz <robin.getz@analog.com>
2021-09-16 16:49:52 +03:00
779a5dba22
HDL Logo: Add
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Add a small logo for branding and documetation purposes.
Signed-off-by: Robin Getz <robin.getz@analog.com>
2021-09-16 16:49:52 +03:00
1766b42a93
ad_mem_asym: Add option to control cascade layout
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Signed-off-by: David Winter <david.winter@analog.com>
2021-09-15 12:27:49 +03:00
12b7fbb3a3
scripts: Add *.gen to clean list
2021-09-14 16:44:23 +03:00
6763ddcda9
spi_engine_execution: Fix cs signal generation
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The cs signal can now accept the IOB TRUE attribute.
2021-09-13 11:39:02 +03:00
cc68bd5198
fmcjesdadc1: Update block design ( #743 )
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Modified the project such that there is only one data path for the ADC data: deleted one of the JESD tpl instances, one of the cpack instances and one of the dma instances.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-09-08 17:19:57 +03:00
0392013bd2
util_tdd_sync: Narrow scope of false path to D pin
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Signed-off-by: David Winter <david.winter@analog.com>
2021-09-08 11:58:24 +03:00
7423ecae14
data_offload: Improve external synchronization
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This commit adds a new synthesis option to the design, that controls
whether an internal clock domain crossing will be generated. Disabling
this option allows you to use a synchronization signal that is
synchronized to the write clock domain externally, and possibly shared
between multiple devices.
The default value retains the old behavior.
Signed-off-by: David Winter <david.winter@analog.com>
2021-09-08 11:58:01 +03:00
0372ce1821
axi_adxcvr:util_adxcvr: Correctly defined resets.
2021-09-08 11:51:59 +03:00
16a93a804b
adrv9001[intel]: Add second pair of DMAs
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fix observations for PR
2021-09-01 15:04:14 +03:00
fec4137046
ad400xx_fmc: Parametrize board select, sampling rate and adc resolution
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fix comments
2021-09-01 15:03:10 +03:00
b7f34f7bd9
adrv9009zu11eg & common/zcu102 : Fix zynqmp ref clock definition
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The derived clocks of the zynqmp core are not calculated correctly due
rounding issues, instead of 100MHz the value of 99999001 is received
causing warnings during system validation.
This can be fixed/worked around with the proper reference clock
definition.
2021-08-20 10:46:09 +03:00
b354d517f5
daq2: Connected loose ad9144 dunf flag that fixes the critical warning
2021-08-20 10:38:52 +03:00
4cf53f373b
Revert "adrv9009zu11eg: Integrate data_offload"
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This reverts commit 78999e154e
2021-08-19 21:43:09 +03:00
f8c82c611d
axi_adrv9001: Add support for symbol operation mode on Xilinx devices
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Add CMOS support for the interface for the following symbol modes on Xilinx devices:
A B C D E F G H
CSSI__1-lane 1 16/8 80(SDR)/160(DDR) 80 - SDR/DDR SDR/DDR->4/2(C=16), 2/1(C=8)
Columns description:
A - SSI Modes
B - Data Lanes Per Channel
C - Serialization factor Per data lane
D - Max data lane rate(MHz)
E - Max Clock rate (MHz)
F - Max Sample Rate for I/Q (MHz)
G - Data Type
H - DDS Rate
CSSI - CMOS Source Synchronous Interface
2021-08-17 15:33:06 +03:00
8afc03abab
jesd204/ad_ip_jesd204_tpl_dac: Intel: Add support for AD916x preset files
2021-08-16 07:22:50 +03:00
1f24344620
Update Quartus version to 20.4
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Update quartus compilation tools from 20.1 to 20.4.
Remove hardcoded version from axi_adrv9001 ip.
2021-08-12 11:15:01 +03:00
b1d2a069e8
adi_make: Update bin build flow for 2020.1 tools
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The 2020.1 Xilinx tools have a different tcl procedures to build the boot.bin
file.
This commit updates the adi_make tcl flow for the new tools. The new
process is not backwards compatible with tools older than 2020 version.
2021-08-10 17:44:30 +03:00
235542cac9
data_offload: Fix support for > 4 GiB of storage
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This commit changes the transfer length register to work in increments of
64 bytes and without offset. The true transfer length can now be
determined by multiplying the value of the transfer_length register with
64.
A value of zero is interpreted as a request for all available storage.
Additionally, this commit fixes an off by one issue that was discovered
during testing of the RX path.
Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
25038ccb4d
data_offload: Fix MEM_SIZE parameter width
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Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
58953ff40d
data_offload: Fix m_axis output stability issue
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Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
2b55c7453b
data_offload: Fix duplicated output samples
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Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
04f2d19d4b
data_offload: Fix data_offload getting stuck on oscillating m_saxis_ready
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Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
0af50d3f72
data_offload: Fix oneshot mode
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Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
66748510ea
data_offload: write_fsm: Always transition out of idle on high init_req
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Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
9faef440b2
data_offload: Bump hdl version
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Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
a89d0e6176
data_offload: Fix AXI register map
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Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
e9e278c898
ad9081_fmca_ebz: Remove bypass gpio
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Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
537a284115
data_offload: Fix readme images
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Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
2178191610
ad9081_fmca_ebz: Switch util_dacfifo to data_offload engine
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Memory requirements are the same as with the dacfifo (1 MiB).
Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
6516b09a31
data_offload: Update README and generic block design
2021-08-06 11:55:24 +03:00
26518cdace
data_offload: Add block diagrams
2021-08-06 11:55:24 +03:00
9b1108ea87
data_offload: Flush the DMA if the transaction size is bigger than the storage
2021-08-06 11:55:24 +03:00
564ef77588
data_offload: Calculate AXI_ADDRESS_LIMIT automatically
2021-08-06 11:55:24 +03:00
c82b0fb420
data_offload: Delete fifo_dst_rlast
2021-08-06 11:55:24 +03:00
4026f2d414
daq2/zc706: PL DDR size is 1GByte
2021-08-06 11:55:24 +03:00
703cc8a17e
data_offload_bd: Calculate the address limit from the address width
2021-08-06 11:55:24 +03:00
0436a82f4e
data_offload: Fix alignment of write last beat and write full
2021-08-06 11:55:24 +03:00
378daf031c
data_offload: Improve timing in regmap
2021-08-06 11:55:24 +03:00
c27a0e4add
data_offload: Fix fifo_dst_ready generation
2021-08-06 11:55:24 +03:00
78999e154e
adrv9009zu11eg: Integrate data_offload
2021-08-06 11:55:24 +03:00
dc910420bd
daq2: Integrate data_offload
2021-08-06 11:55:24 +03:00
4c03580156
data_offload: Add integration process for Xilinx carriers
2021-08-06 11:55:24 +03:00
86b611c1f7
data_offload: Initial commit
2021-08-06 11:55:24 +03:00
stefan.raus
Mihaita Nagy
David Winter
AndreiGrozav
Adrian Costina
Robin Getz
sergiu arpadi
Iacob_Liviu
hotoleanudan
Filip Gherman
Laszlo Nagy
alin724
Istvan Csomortani