Commit Graph

6 Commits (8e243b6d32a019d5cc4119f3b150db10d32e1317)

Author SHA1 Message Date
Matt Blanton 1e04b2e2f2 jesd204_rx: Add RX frame alignment character check
Add support for RX frame alignment character checking when scrambling is enabled and
for link reset on misalignment.
Add support for xcelium simulator to jesd204/tb
2020-07-31 11:43:41 +03:00
Lars-Peter Clausen d72fac4b1e Add missing timescale annotations
For consistent simulation behavior it is recommended to annotate all source
files with a timescale. Add it to those where it is currently missing.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-10-17 10:32:47 +03:00
Lars-Peter Clausen 840dd221b7 jesd204_rx: Count errors only once per character
Typically only one of the character error conditions is true at a time. And
even if multiple errors were present at the same time we'd only want to
count one error per character.

For each character track whether at least one of the monitored error
conditions is true. Then count the number of characters for which at least
one error condition occurred. And finally add that sum to the total numbers
of errors.

This results in a slightly better utilization.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-16 09:34:36 +02:00
Lars-Peter Clausen d3b548de65 jesd204_rx: Reset lane error statistics when link is disabled
When the link is explicitly disabled through the control interface reset
the error statistics counter.

There is usually little benefit to preserving until after the link has been
disabled. If software is interested in the values it can read them before
disabling the link. Having them reset makes the behavior consistent with
all other internal state of the jesd204 RX peripheral, which is reset when
the link is disabled.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-16 09:34:36 +02:00
Adrian Costina 3b9f733408
jesd204: Add RX error statistics (#98)
* jesd204: Add RX error statistics

Added 32 bit error counter per lane, register 0x308 + lane*0x20

On the control part added register 0x244 for performing counter reset and counter mask
Bit 0 resets the counter when set to 1
Bit 8 masks the disparity errors, when set to 1
Bit 9 masks the not in table errors when set to 1
Bit 10 masks the unexpected k errors, when set to 1

Unexpected K errors are counted when a character other than k28 is detected. The counter doesn't add errors when in CGS phase

Incremented version number
2018-05-07 15:33:00 +03:00
Istvan Csomortani 09ff1f3a77 jesd204: Fix file names
All the file names must have the same name as its module. Change all the
files, which did not respect this rule.
Update all the make files and Tcl scripts.
2018-04-11 15:09:54 +03:00