Commit Graph

288 Commits (8e689f459435db05508dd48cc51171117c8c32bb)

Author SHA1 Message Date
Rejeesh Kutty 8e689f4594 pzsdr1- lvds/cmos constraints 2016-04-11 16:00:18 -04:00
Rejeesh Kutty 68bc647472 pzsdr1- ddr board delays update 2016-04-06 15:30:27 -04:00
Istvan Csomortani 255b0ebd40 util_dacfifo: Add dac_xfer_out control
The dac_xfer_out control signal is asserted while the DAC reads back data. Should be connected to upack/dma_xfer_in.
2016-03-29 16:50:00 +03:00
Istvan Csomortani 373481360b util_dacfifo: Add a bypass option to the FIFO 2016-03-21 14:14:43 +02:00
Rejeesh Kutty 561412e322 pzsdr-cmos swap 2016-03-11 11:25:58 -05:00
Rejeesh Kutty 18f30c8dc8 pzsdr- cmos/lvds split 2016-03-04 10:39:48 -05:00
Rejeesh Kutty a2374f64bf pzsdr- cmos/lvds split 2016-03-04 10:39:48 -05:00
Rejeesh Kutty e012d0519b Merge remote-tracking branch 'origin/hdl_2015_r2' into dev 2016-02-26 13:39:39 -05:00
Rejeesh Kutty f6e64e42b0 kcu105: add ethernet idelaycntrl 2016-02-26 13:19:49 -05:00
Adrian Costina 377461e0d4 Merge branch 'hdl_2015_r2' into dev 2016-02-19 14:15:27 +02:00
Adrian Costina 0f37dd6424 fmcjesdadc1: Fixed project
- changed system_project.tcl so that all base designs to be included
- changed DMA properties to take into consideration the new parameter names
- changed reset bridges to asynchronous
- increased maximum burst size of the DMA bridge
- changed the data_width of the memory bus to 256, as with 512 timing violations may occur
- changed base addresses for the base system to be the same as in the previous release
2016-02-19 14:09:57 +02:00
Adrian Costina 43e03ca6f7 arradio: Updated project
- made the reset bridges asynchronous
- connected the arradio gpio to the CPU interconnect
2016-02-16 14:50:23 +02:00
Adrian Costina ad9ecbbbb6 daq2: Updated a10gx project to quartus 15.1.1 2016-02-05 17:43:05 +02:00
Rejeesh Kutty b147e9c94a pzsdr1- updates 2016-02-02 12:33:01 -05:00
Rejeesh Kutty 170295161f pzsdr1- xdc 2016-01-26 11:19:00 -05:00
Rejeesh Kutty 44a382fc69 pzsdr1-added 2016-01-25 15:33:34 -05:00
Lars-Peter Clausen d2b26720e6 common: microzed: Add clock, reset and interrupt support
In order for the base project to be usable by other projects it needs to
create the clock, reset and interrupt signals that are expected to exist.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-01-13 20:32:26 +01:00
Lars-Peter Clausen 426490c394 common: Rename uzed to microzed
Everybody calls the MicroZed microzed in their projects. Don't deviate from
that to avoid potential confusion.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-01-13 20:18:57 +01:00
Rejeesh Kutty c397787001 uzed: updates 2016-01-11 15:36:01 -05:00
Rejeesh Kutty a610ebb413 uzed: zed-copy 2016-01-11 13:53:22 -05:00
Rejeesh Kutty 650d426301 a10gx/base: set gpio to 32 2015-12-11 10:14:37 -05:00
Rejeesh Kutty f1b6577447 a10gx/base: separate gpio in/out 2015-12-10 16:04:54 -05:00
Adrian Costina a0e67aad56 c5soc: Updated common design 2015-11-24 13:22:01 +02:00
Rejeesh Kutty 597e9eae84 pzsdr: added ad9361 clock out 2015-11-16 15:53:29 -05:00
Adrian Costina 83399ef6ee a10gx: Updated common project to work with Linux (enabled MMU) 2015-11-04 13:35:52 +02:00
Adrian Costina 9d2b8809df Makefiles: Updated Makefiles 2015-10-23 10:44:27 +03:00
Rejeesh Kutty 14bccb6062 pzsdr/ccfmc- rf card/tdd only on fmc 2015-09-22 15:54:53 -04:00
Rejeesh Kutty 25f3f05c22 pzsdr- breakout + fmc updates 2015-09-18 15:33:50 -04:00
Rejeesh Kutty caec400378 pzsdr- make module default 2015-09-18 13:22:01 -04:00
Rejeesh Kutty 236854c26f pzsdr-cc-fmc updates 2015-09-18 12:46:42 -04:00
Rejeesh Kutty 3ef94d559c rfsom renamed to pzsdr 2015-09-18 11:18:59 -04:00
Rejeesh Kutty 52d3f189a0 rfsom renamed to pzsdr 2015-09-18 11:18:01 -04:00
Adrian Costina 0021c7869d kc705: Deactivated narrow burst support, as it's not needed 2015-09-16 19:02:17 +03:00
Adrian Costina d81d8238a9 kc705: Updated mig project file 2015-09-08 16:42:23 +03:00
Rejeesh Kutty 01c0fdc809 daq2/a10gx- ethernet fix 2015-09-02 14:31:15 -04:00
Istvan Csomortani 1ecd615f92 common/mitx045 : Fix the vdma interface of axi_hdmi_core 2015-09-02 16:33:30 +03:00
Rejeesh Kutty a67ae238f8 rfsom-ps7- ddr settings 2015-08-31 15:39:45 -04:00
Rejeesh Kutty 212235189f hdmi-tx- signal name changes 2015-08-28 13:48:33 -04:00
Rejeesh Kutty 0e20277bc1 hdmi-tx- signal name changes 2015-08-28 13:48:33 -04:00
Rejeesh Kutty 93fe70790d hdmi-tx- signal name changes 2015-08-28 13:48:33 -04:00
Rejeesh Kutty 810fced1ec hdmi-tx- signal name changes 2015-08-28 13:48:33 -04:00
Rejeesh Kutty 6e90ba24e4 rfsom- add rgmii iodelay constraints 2015-08-27 16:26:17 -04:00
Rejeesh Kutty 3953ab5e22 rfsom- rgmii upgrade 2015-08-27 11:41:55 -04:00
Rejeesh Kutty 74a6e33f2d kcu105: 2015.2.1 updates 2015-08-25 09:12:36 -04:00
Rejeesh Kutty 4eb28592c8 kcu105: 2015.2.1 updates 2015-08-25 09:12:32 -04:00
Istvan Csomortani 77e2eb7364 projects/common: Fix parameter name for xilinx core axi_gpio
Parameter C_GPDATA_WIDTH is changed to C_GPIO_WIDTH.
2015-08-25 10:07:11 +03:00
Istvan Csomortani d3e090da3d projects/common: Upgrade Xilinx's IP cores
To update the projects to Vivado 2015.2 the following IP cores were upgraded:
    + microblaze 9.4 to microblaze 9.5
    + axi_ethernet 6.2 to 7.0
    + mig 6.1 to 7.0
2015-08-25 10:03:49 +03:00
Istvan Csomortani 203d7cb470 projects/common: Cosmetic changes. 2015-08-25 09:58:32 +03:00
Istvan Csomortani f08305c979 adv7511_ac701: Fix axi_ethernet core's port connections 2015-08-25 09:54:19 +03:00
Istvan Csomortani af8a48d90e projects: Fix broken parameters at the common block designs.
Fix parameter names for axi_spdif_tx and axi_i2s_adi core instantiations.
2015-08-25 09:25:24 +03:00