Those were added by mistake. It does not seem to be legal Verilog, but for
some reason Vivado accepts it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
ffff and 0000 are always reserved control characters when using embedded
syncs. So make sure that we never have them in the pixel data, even when
running in full-range mode.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Add a control bit to the register map that allows to bypass the chroma
sub-sampler in the axi_hdmi_tx core. This is primarily interned to be used
to send the test-pattern directly to the HDMI transmitter without modifying
it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently the axi_hdmi_tx core constraints marks all its clocks asynchronous
to all other clocks in the system. This is a bit unfortunate as these
constraints are not restricted to the axi_hdmi_tx, but affect all cores in
the system, some of which might actually have timing constraints on CDC
paths.
The proper way to fix this is to add constraints for the axi_hdmi_tx core
CDC paths. For now only mark the interface clock asynchronous to the HDMI
clock, as this is easy to do and an improvement over the current situation,
as other cores are no longer affected.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Clean ran for a project will clean only the project files.
Clean-all ran for a project will clean also the library files on which the project depends.
The clean commands will only remove specific files and directories.
The top Makefile allows several options(per suggestion from jameyhicks):
make fmcomms1.zed will run "make all" in projects/fmcomms1/zed/
make clean will run "make clean" for all the projects
make clean-all will run "make clean" for all the projects and libraries
make lib will run "make all" for the library files
Instead of just marking all clock domains as asynchronous set the
appropriate constraints for each CDC path.
For single-bit synchronizers use set_false_path to not constraint the path
at at all.
For multi-bit synchronizers as used for gray counters use set_max_delay with
the source clock period domain to make sure that the signal skew will not
exceed one clock period. Otherwise one bit might overtake another and the
synchronizer no longer works correctly.
For multi-bit synchronizers implemented with hold registers use
set_max_delay with the target clock period to make sure that the skew does
not get to large, otherwise we might violate setup and hold time.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Istvan Csomortani
Rejeesh Kutty
Adrian Costina
Lars-Peter Clausen