Rejeesh Kutty
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5d6b018b2b
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ad9162- add iq swap
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2017-04-26 20:54:47 -04:00 |
Istvan Csomortani
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1c23cf4621
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all: Update verilog files to verilog-2001
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2017-04-13 11:59:55 +03:00 |
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Istvan Csomortani
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c1bdfca4c3
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library: Delete all adi_ip_constraint process call
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2017-04-06 12:36:47 +03:00 |
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Istvan Csomortani
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c46989e4e8
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Makefile: Update Makefiles for libraries
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2017-03-30 18:33:22 +03:00 |
Istvan Csomortani
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873fbfd6d7
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library: Update scripts with new constraints
Update all IPs tcl scripts with the new constraints files.
Refer to commit 335fef0.
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2017-03-30 16:16:02 +03:00 |
Adrian Costina
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8ebc8fe4e2
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updated makefiles
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2016-12-09 23:06:41 +02:00 |
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Rejeesh Kutty
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b85a282748
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fmcomms11- lane swap
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2016-11-16 10:26:47 -05:00 |
AndreiGrozav
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9d6c93a5d8
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Fix warnings
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2016-11-14 15:17:15 +02:00 |
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Istvan Csomortani
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8dbfe9258f
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axi_ad9162: Delete duplicated port
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2016-10-21 13:47:01 +03:00 |
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AndreiGrozav
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43ee917d53
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Add up_dac_channel missing connections
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2016-10-12 13:20:26 +03:00 |
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Rejeesh Kutty
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c98e2e95dd
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ad9162- xcvr updates
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2016-09-26 15:21:45 -04:00 |
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Rejeesh Kutty
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f6c7aa9005
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library- dac parameter changes
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2016-09-23 16:15:59 -04:00 |
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Istvan Csomortani
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913eafed48
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up_drp : Update the DRP interface to support Altera platforms
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2016-09-21 15:00:45 +03:00 |
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Istvan Csomortani
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0cd608a7e2
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lib_refactoring: Update Make files
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2016-08-08 16:38:38 +03:00 |
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Istvan Csomortani
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df36902713
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lib_refactoring: Fix path of the IO macros
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2016-08-08 15:07:19 +03:00 |
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Adrian Costina
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d60bce654c
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Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
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2016-08-05 15:16:04 +03:00 |
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Rejeesh Kutty
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3a1ecb7463
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ad9162- support iq mode
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2016-07-21 11:58:03 -04:00 |
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Rejeesh Kutty
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48762519b5
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make updates
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2016-07-06 15:02:00 -04:00 |
Shrutika Redkar
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d931b2ee64
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ad9162 core verilog files
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2016-06-30 10:24:01 -04:00 |