9a36075324
moved fmcomms5
2014-05-19 13:49:49 -04:00
f73819f4d4
zc706: pl ddr3 initial checkin
2014-05-13 16:19:53 -04:00
f3f8374c75
ad9671: 2lane version
2014-05-08 18:33:26 -04:00
c5b3dd3643
vc707 base : tcl update
...
- Added missing address space
- Connect the sys_audio_clkgen/reset
2014-05-08 12:30:25 +03:00
3ac1da178e
kcu105: sane except for ddr4/ethernet
2014-05-06 15:39:05 -04:00
51c0ee1e20
ml605: tcl updates
2014-05-06 09:29:21 -04:00
e7cbaca216
ml605: initial checkin
2014-05-05 11:24:12 -04:00
53af7f3c1f
ml605: initial checkin
2014-05-05 11:20:26 -04:00
4d4f66fbdd
a5soc: increase pipeline for qsys
2014-05-04 10:38:53 -04:00
b55d0d7ad1
a5soc: constraints for false paths
2014-04-30 16:14:30 -04:00
a10043c4f4
kcu105: base complete with ethernet errors
2014-04-30 14:41:43 -04:00
ef60cce15e
kcu105: added
2014-04-30 14:41:40 -04:00
be69c0c330
kcu105: initial checkin
2014-04-30 14:41:39 -04:00
9900a56fa5
kcu105: initial checkin
2014-04-30 14:41:37 -04:00
0b1ce14842
a5soc: basic hardware build
2014-04-30 12:40:27 -04:00
99d66e7580
a5soc: initial-copy version
2014-04-30 12:40:26 -04:00
681e4239df
ad9671/a5gt: subclass-0 version
2014-04-28 21:31:21 -04:00
06873aeddb
ad9671/a5gt: subclass-0 version
2014-04-28 21:31:20 -04:00
d66f256f1c
9671/a5gt: 9671-sc1 version
2014-04-28 21:31:19 -04:00
f55288ef5d
ad9671: altera - base changes
2014-04-28 21:31:18 -04:00
2e7bf190b5
initial checkin-9250 copy
2014-04-28 21:31:15 -04:00
01de117b5f
motor_control: Changed controller to PID controller. Some estetic changes
2014-04-28 17:57:51 +03:00
dfc2bba335
ad9671: updates to allow default adc setup routines
2014-04-23 16:39:28 -04:00
a1bcf345c6
ad9671: fix spi connections
2014-04-21 13:46:44 -04:00
213e852e11
motor_control: Initial commit
2014-04-18 18:57:18 +03:00
ba44ee63be
fmcomms1: modified the fmcomms1_bd.tcl to make it compatible with latest wfifo
2014-04-14 17:04:04 +03:00
179d6d601c
adi_board.tcl : Use 'global' instead of '$::'
2014-04-14 11:45:35 +03:00
38126c404c
usdrx1: spi signal definitions
2014-04-11 14:28:23 -04:00
06b28d2e24
ad9671: compile fixes
2014-04-11 14:28:22 -04:00
e92e6b2fd5
ad9671_fmc: changed for ad9671-fmc
2014-04-11 14:28:21 -04:00
72e318a247
ad9671_fmc: initial checkin
2014-04-11 14:28:20 -04:00
99ef34936f
Merge branch 'master' of https://github.com/analogdevicesinc/hdl
2014-04-11 18:14:08 +03:00
d0f04fd788
fmcomms1: Commit AC701 and VC707 projects
2014-04-11 17:35:25 +03:00
c718169f27
adi_board.tcl : Fix the address assignment command
...
A lot of cores have more than one address segments, therefor need
to filter out the segment of the axi lite interface
2014-04-11 16:14:56 +03:00
cf5b9b51fd
adi_board.tcl : Fix spi ports and hp clocks
2014-04-11 15:31:12 +03:00
37e2059fd0
adi_board.tcl : General update
...
- Split the adi_dma_interconnect to two procedure:
adi_dma_interconnect and adi_hp_assign
- Fix the adi_spi_core
- Fix the adi_interconnect_lite
2014-04-10 18:29:14 +03:00
96541f0a7f
usdrx1: zc706 updated for usdrx1
2014-04-10 11:05:13 -04:00
6f36f74eea
usdrx1: common board files
2014-04-10 11:05:11 -04:00
ac1c145a61
usdrx1: initial checkin
2014-04-10 11:05:10 -04:00
dc7b3e085c
axi_dmac: Fix issues with non 64-bit AXI masters
...
Make sure that the address generator behaves correctly when the buswidth is not
64-bit. Also since the source and destination can have different widths add
separate parameters for source and destination address alignment.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 14:54:22 +02:00
9d19145713
Merge branch 'master' of https://github.com/analogdevicesinc/hdl
2014-04-10 10:50:53 +03:00
5aac9d7288
FMCOMMS2 added sync option
...
Added signals to allow synchronisation of multiple AD9361.
2014-04-10 10:46:42 +03:00
fbfd658f0d
zc706: added pl ddr3 mig
2014-04-09 15:58:12 -04:00
e73952a694
ad9467 : initial checkin
2014-04-09 17:34:40 +03:00
5b0e37b97a
adi_project.tcl : Modify implementation strategy
...
- Change implementation strategy to Performance Explore.
At some projects, this could prevent timing issues, it not
increase the overall implementation time in a dramatic way.
2014-04-07 15:02:38 +03:00
33979fc533
fixes to improve timing - fifo for clock domain transfers
2014-04-04 13:49:53 -04:00
6a19b34a00
a5gt: added tightly coupled memory
2014-04-03 20:50:17 -04:00
04ab34c8ed
a5gt: ethernet assignments
2014-04-03 20:50:16 -04:00
12e5cc91bd
make signaltap/timing part of the flow
2014-04-03 20:50:15 -04:00
d0a8b4a63c
kc705,common: Mem_interconnect maximize performance
...
For FMCOMMS1, when both the ADC and DAC DMAs are active, the system was
unstable. With this fix, it the system seems to be stable.
2014-04-03 15:59:33 +03:00
Rejeesh Kutty
Istvan Csomortani
Adrian Costina
ATofan
Lars-Peter Clausen
Istvan Csomortani