Rejeesh Kutty
91765fdd82
daq2+base: board tcl updates
2015-03-05 10:56:36 -05:00
Rejeesh Kutty
7bf4141a3f
daq2+base: board tcl updates
2015-03-05 10:56:36 -05:00
Rejeesh Kutty
bf1388b05e
kcu105: rev.d changes
2015-03-04 12:43:04 -05:00
Rejeesh Kutty
4f918cdce9
2014.4.1 ultrascale updates
2015-02-26 16:10:57 -05:00
Rejeesh Kutty
847c2e049a
kcu105: removed lutram constraints
2015-02-26 16:09:55 -05:00
Istvan Csomortani
1613f7fb41
cftl_cip: Add util_pmod_fmeter IP to library
...
Frequency meter IP for CN0332.
2015-02-23 17:20:12 +02:00
Lars-Peter Clausen
abde4048e0
fmcomms1: Add extra AXI slice on ADC DMA path
...
Add a extra AXI slice on the ADC DMA data path to the HP interconnect to
improve the timing.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-20 16:43:45 +01:00
Rejeesh Kutty
b9d16a7eb1
scripts: renaming board parameters
2015-02-20 09:12:30 -05:00
Rejeesh Kutty
288f5378ff
rfsom: schematic changes
2015-02-18 14:32:41 -05:00
Rejeesh Kutty
93e2bcd911
rfsom: schematic changes
2015-02-18 14:32:30 -05:00
Rejeesh Kutty
383cf3b3a3
rfsom: schematic changes
2015-02-18 14:32:20 -05:00
Rejeesh Kutty
d2e9b1fe03
rfsom: schematic changes
2015-02-18 14:32:04 -05:00
Istvan Csomortani
3113abf038
cftl_cip: Add gpio counter for CN0332
...
Add a counter core to the design, to support the CN0332 pmod with a speed sensor.
Change a naming for the custom cores.
2015-02-18 18:24:46 +02:00
Rejeesh Kutty
e111e1336e
conflicts-
2015-02-06 22:14:21 -05:00
Istvan Csomortani
2d607d765b
cftl_cip: Add a clock input to the device core, for the SPI clock.
...
This clock can be adjustable from the system_project.tcl
2015-02-04 14:55:17 +02:00
Rejeesh Kutty
996e1b7970
rfsom: constraint updates
2015-02-03 14:20:34 -05:00
Adrian Costina
fd2ab02174
cftl_std: Added in the constraint file comments regarding supported CFTLs
2015-01-29 16:27:43 +02:00
Istvan Csomortani
d69d105b5d
vc707_common: Fix address mapping
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The axi_ethernet/eth_buf/S_AXI_2TEMAC address space and axi_ethernet/eth_mac/s_axi/Reg address
segment does not exist in 2014.4.
2015-01-29 12:22:06 +02:00
Istvan Csomortani
e8ff30119d
vc707_xdc: Delete unnecessary clock definition
2015-01-29 11:39:10 +02:00
Istvan Csomortani
6c8ea24f20
common: Update VC707 base design to 2014.4
2015-01-28 16:24:52 +02:00
Istvan Csomortani
e1d8dd10a9
daq2: Initial check in of the VC707 based project
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NOTE: Can not communicate with the clock chip, rx/tx PLL not locking.
2015-01-28 16:24:06 +02:00
Istvan Csomortani
659e0cca4e
cftl_cip: Initial check in.
...
Project cftl_cip supports the following Circuits from the Lab pmods:
+ EVAL-CN0350-PMDZ
+ EVAL-CN0335-PMDZ
+ EVAL-CN0336-PMDZ
+ EVAL-CN0337-PMDZ
Note: Additional testing needed!
2015-01-23 18:29:32 +02:00
Adrian Costina
463a3bbc88
cftl_std: Updated project. Switched to PS7 gpio. Renamed signals.
2015-01-23 14:11:33 +02:00
Adrian Costina
9672271155
fmcjestadc1: a5gt: Updated project to work with linux and fixed ethernet
...
- added phy reset mechanism for proper functioning of the ethernet
- not all DDR is accesible, as NIOS2 can't access it with MMU enabled
2015-01-23 13:30:56 +02:00
Adrian Costina
5a77ab0161
a5gt:common: Added phy reset signal from ethernet in pin assignments
2015-01-23 12:31:41 +02:00
Adrian Costina
050f17e034
a5gt3: common: corrected naming in pin assignments. added reset signal from FPGA2
2015-01-23 12:30:16 +02:00
Rejeesh Kutty
72e89852b6
daq2/kc705: 2014.4 updates
2015-01-14 12:58:08 -05:00
Rejeesh Kutty
024d9e7309
replace export hardware -- hwdef/sysdef
2015-01-13 13:40:21 -05:00
Rejeesh Kutty
03988f1c9f
kcu105-daq2-2014.4-- intermediate fixes
2015-01-13 13:40:20 -05:00
Rejeesh Kutty
b595cce697
kcu105-daq2-2014.4-- intermediate fixes
2015-01-13 13:40:18 -05:00
Rejeesh Kutty
b0b4bfe531
kcu105-daq2-2014.4-- intermediate fixes
2015-01-13 13:40:17 -05:00
Adrian Costina
47871287f3
kc705: Updated base project with linear flash. Updated all depending projects
2015-01-13 10:19:07 +02:00
Rejeesh Kutty
b9e2c5659f
fmcomms2: 2014.4
2015-01-09 14:12:54 -05:00
Rejeesh Kutty
9e64df917c
daq2: 2014.4
2015-01-09 14:12:53 -05:00
Rejeesh Kutty
65d9f08763
zc706: mig 2014.4
2015-01-09 14:12:52 -05:00
Rejeesh Kutty
868df1aac8
zc706: mig 2014.4
2015-01-09 14:12:51 -05:00
Rejeesh Kutty
0258afbadc
board: add ddr seg variable
2015-01-09 14:12:50 -05:00
Adrian Costina
22d881981e
cftl_std: Renamed cftl standard project
2015-01-09 19:44:13 +02:00
Rejeesh Kutty
debbe31713
Merge remote-tracking branch 'origin/master' into dev
2015-01-09 11:12:56 -05:00
Rejeesh Kutty
117686f352
ad9739a: updates for ad9739a
2015-01-09 10:54:50 -05:00
Rejeesh Kutty
785d3a4ae3
ad9739a: updates for ad9739a
2015-01-09 10:54:40 -05:00
Rejeesh Kutty
e8d0782a2e
ad9739a: updates for ad9739a
2015-01-09 10:54:22 -05:00
Rejeesh Kutty
baea2090d6
ad9739a: updates for ad9739a
2015-01-09 10:54:12 -05:00
Rejeesh Kutty
c9b6411e86
ad9739a: updates for ad9739a
2015-01-09 10:54:00 -05:00
Adrian Costina
51e6d0888a
cftl_xil_zed: Initial commit for common platform used with CFTL circuits
...
This common platform uses PS7 SPI and I2C to communicate with different chips.
On different connectors different pin configurations are supported:
- On connector JA, a spi interface and a 2 pin GPIO
- On connector JB, a I2C interface
- On connector JC, a spi interface with 2 chip selects
2015-01-09 17:47:29 +02:00
Rejeesh Kutty
a9cc8f6c91
ad9739a_fmc: added
2015-01-08 10:35:59 -05:00
Istvan Csomortani
a170ebfb82
imageon: Initial commit
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Initial commit of the IMAGEON project for ZC706. NOT tested.
2015-01-08 17:01:22 +02:00
Adrian Costina
f566268db5
zed_common: Updated common to 2014.4
2015-01-08 11:59:26 +02:00
Adrian Costina
f6df66ea06
motcon2_fmc: initial commit of the base design
...
Because vivado crashes when adding the speed detector, it's not part of this commit.
The controller is also not part of this commit
2015-01-08 11:57:22 +02:00
Rejeesh Kutty
eb569b991d
dmafifo- remove util fifo setup
2015-01-06 16:23:14 -05:00