3 Commits (9180d4dd391853ebd9a4e0a88db1faa9a8fcd562)

Author	SHA1	Message	Date
Istvan Csomortani	103cbe73dc	intel/adi_jesd204: Add support for external core clock ... In Subclass 1 mode, we need to use a separate clock (device clock) to drive the link and transport layer of the interface. Implement the required infrastructure for this scenario. The clock domain crossing will be done in by the TX|RX_FIFO in the PCS.	2019-10-02 15:32:17 +03:00
Istvan Csomortani	5329458a62	library/scripts: Rename adi_ip_alt.tcl to adi_ip_intel.tcl	2019-06-29 06:53:51 +03:00
Istvan Csomortani	79b6ba29ce	all: Rename altera to intel	2019-06-29 06:53:51 +03:00