Commit Graph

7 Commits (91b199a907651a3195676da10eed71258e922fb7)

Author SHA1 Message Date
Adrian Costina c32b4b02f3 sync_bits: Change I/O names of wires "in" and "out" for VHDL users 2019-04-23 18:03:23 +03:00
Lars-Peter Clausen d72fac4b1e Add missing timescale annotations
For consistent simulation behavior it is recommended to annotate all source
files with a timescale. Add it to those where it is currently missing.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-10-17 10:32:47 +03:00
Lars-Peter Clausen 965d3b4c79 util_cdc: Silence warnings about unused sequential logic
Some parts of the util_cdc library rely on dead logic elimination to remove
unused logic. Unfortunately with newer Vivado versions this results in
warnings about unused sequential elements being removed. Like:

	WARNING: [Synth 8-6014] Unused sequential element cdc_sync_stage1_reg was removed.

To avoid this encase the logic in generate blocks that makes sure they are
not generated when not needed.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-06-06 09:38:19 +02:00
Istvan Csomortani 425e803364 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
Istvan Csomortani fb6035f0dc util_cdc: Update to verilog-2001 coding standard 2017-08-07 11:26:17 +03:00
Istvan Csomortani 50cdb6db67 Merge branch 'jesd204' into dev 2017-05-31 20:44:32 +03:00
Lars-Peter Clausen 01aea161fa Create CDC helper library
Move the CDC helper modules to a dedicated helper modules. This makes it
possible to reference them without having to use file paths that go outside
of the referencing project's directory.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00