When phase alignment is active, the PFD frequency value should be used
as outclk1 actual frequency.
The configuration interface of the fPLL does not support fractional values.
If the reference clock is fractional, the tool will throw an error that requirement
above is not respected.
Round up the reference clock for the SERDES and the lane rate in order to
overcome this issue, until it's not fixed by Intel.
The reconfiguration interface for the Stratix10 XCVR has a different
address width. Prepare the register map layout of the project to support
this new architecture.
Istvan Csomortani
Dragos Bogdan
Laszlo Nagy
Adrian Costina