961ebe0cc2
projects: Update .v files according to guideline
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Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
4f4825a3df
projects:daq2:common: fix adi_tpl_jesd204_rx_create error. ( #952 )
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(\ character has to be removed or a blank line inserted before ad_ip_parameter)
Fix for : 0b8585a6f
2022-06-06 08:53:07 +03:00
0b8585a6f1
PN mismatch DAQ2, DAQ3 and FMCJESDADC1 fix ( #950 )
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The AD9680 is a dual 14-bit ADC.
Software sets the output format to offset binary before performing the PN tests.
2022-06-02 14:09:36 +03:00
97b92565b2
Makefile: Replace util_fifo2axi_bridge with util_hbm
2022-04-28 14:31:32 +03:00
0e55583a63
daq2: Do not set AXI address width for DO
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Address size and memory ranges are automatically computed by the
external storage interfacing IP (util_hbm) based on the storage size and
base address so this parameter is redundant.
2022-04-28 14:31:32 +03:00
5a33c44511
daq2/zc706: Update to new DO storage
2022-04-28 14:31:32 +03:00
530aca9754
daq2: Parameterize JESD204 configuration values
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Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line for the Xilinx FPGAs in the project.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2022-01-20 12:54:03 +02:00
63b6711cfa
start adding some doc to the ./projects directory
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This adds a Readme.md to each project directory with pointers to project
documentation in the wiki, and the drivers (if they exist). This will
help with some autogenerated doc in the wiki, that is generated with the
innovatily named "wiki_summary.sh" shell script that parses through
these Readme.md files, and generates a summary table.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Iacob Liviu Mihai <liviu.iacob@analog.com>
2021-11-10 14:01:06 +02:00
58c1d2e3b2
projects: fixed xcvr clocks that generated critical warning
2021-11-09 12:40:14 +02:00
d4126739b4
projects: remove hardcoded div_clk from xcvr
2021-10-27 12:11:22 +03:00
ff090b60ef
daq2/zcu102: Fix the ad9144 data offload to use internal BRAM
2021-10-15 15:03:22 +03:00
3640c2b584
daq2/kcu105: Fix the ad9144 data offload to use internal BRAM
2021-10-15 15:03:22 +03:00
6ad54c1056
daq2/kc705: Fix the ad9144 data offload to use internal bram
2021-10-15 15:03:22 +03:00
907cd613aa
daq2/zc706: Increase BRAM utilization to 52%
2021-10-15 15:03:22 +03:00
51b643b978
Makefile: Fix misc makefiles from projects and library
2021-10-05 14:24:48 +03:00
591a23156b
Makefiles: Update header with the appropriate license
2021-09-16 16:50:53 +03:00
b354d517f5
daq2: Connected loose ad9144 dunf flag that fixes the critical warning
2021-08-20 10:38:52 +03:00
4026f2d414
daq2/zc706: PL DDR size is 1GByte
2021-08-06 11:55:24 +03:00
dc910420bd
daq2: Integrate data_offload
2021-08-06 11:55:24 +03:00
6f2f2b8626
makefile: Regenerate make files
2021-01-20 01:02:56 +02:00
acbbd4636a
sysid: Upgrade framework, header/ip are now at 2/1.1.a
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Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
2021-01-20 01:02:56 +02:00
9093a8c428
library: Move ad_iobuf to the common library, as it's not Xilinx specific
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Updated all system_project and Makefiles
2020-11-02 16:13:35 +02:00
37254358dd
makefile: Regenerate make files
2020-10-20 12:51:10 +03:00
d8ab27b2af
sysid: Remove cstring init string
2020-09-30 19:12:24 +03:00
9cac38017b
daq2/a10soc: Set optimization mode to high performance effort
2020-09-25 12:56:14 +03:00
3241924d14
sysid_intel: Added sysid to intel projects
2020-09-11 15:46:06 +03:00
8818089015
a10soc: Reconfiguration interface address width improvement
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The reconfiguration interface's address width is different in various
architectures. Define the required address width in system_qsys.tcl.
2020-09-09 14:15:37 +03:00
b54effc9c9
daq2/a10gx: Set optimization mode to aggressive performance
2020-08-17 10:43:03 +03:00
02ada3bbf7
a10gx: Delete input/output delay definitions
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All input and output delays should be referenced to a virtual clock.
If the input and output delays reference base clocks or PLL clocks rather than
virtual clocks, the intra- and inter-clock transfer clock uncertainties,
determined by derive_clock_uncertainty, are incorrectly applied to the I/O ports.
See mnl_timequest_cookbook.pdf for more info.
2020-08-11 10:14:18 +03:00
1c907b9248
daq2/a10gx: Use the default optimization mode
2020-08-11 10:14:18 +03:00
f3142a6a7a
adi_project_intel: set_interconnect_requirment command is deprecated
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Use set_domain_assignment to set up the maximum pipeline stages for the
main interconnect.
2020-08-11 10:14:18 +03:00
137c31db1d
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-18 15:45:19 +03:00
299273f5a1
daq2/intel: Update project to use generic JESD204B TPL
2020-06-18 15:45:19 +03:00
e22016de4c
adrv9371/daq2/daq3:kcu105: patch GTH3 CPLL parameters
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Update GTH3 parameters according to a 10Gbps link from the Transceiver
Wizard.
2019-10-08 10:38:46 +03:00
aa5fdf903e
Makefile: Update makefiles
2019-08-26 16:58:01 +03:00
0680e44330
system_id: deployed ip
2019-08-06 16:53:11 +03:00
6655829bc7
daq2: VC707: Remove project
2019-07-22 13:25:46 +01:00
04ce10a570
cosmetics: Change Altera to Intel in comments
2019-06-29 06:53:51 +03:00
6e6f1347d7
project/scripts: Rename adi_project_alt.tcl to adi_project_intel.tcl
2019-06-29 06:53:51 +03:00
a589753d92
project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl
2019-06-29 06:53:51 +03:00
43725429ac
adi_project: Rename the process adi_project_xilinx to adi_project
2019-06-29 06:53:51 +03:00
ec67a381e4
adi_project: Rename the process adi_project_altera to adi_project
2019-06-29 06:53:51 +03:00
79b6ba29ce
all: Rename altera to intel
2019-06-29 06:53:51 +03:00
019390f9bf
block_design: Updates with new reset net variables
2019-06-11 18:13:06 +03:00
7960b00684
block_design: Update with new clock net variables
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Using the new clock net variables in all Xilinx block designs.
2019-06-11 18:13:06 +03:00
70b7d69ff8
whitespace: Delete all trailing white spaces
2019-06-07 10:20:15 +03:00
089cd882bc
daq2:qsys: use bundled AXIS interface
2019-05-16 13:27:19 +03:00
7f16f823ff
Revert "axi_dmac: add tlast to the axis interface for Intel"
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This reverts commit e2c75c015f
2019-05-16 13:27:19 +03:00
d894c30c2d
Remove deprecated/unused parameters
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adrv9009
adrv9371x
arradio
daq2
daq3
fmcomms2
fmcomms5
2019-03-30 11:26:11 +02:00
9b048f1a0e
daq2: update adcfifo/dacfifo
2019-01-23 14:45:45 +02:00
Iulia Moldovan
PopPaul2021
Laszlo Nagy
Dan Hotoleanu
Robin Getz
LIacob106
Mihaita Nagy
Adrian Costina
Istvan Csomortani
Sergiu Arpadi
AndreiGrozav