Commit Graph

195 Commits (93897b4cb5546fe925e80ae55900b38c8c65a929)

Author SHA1 Message Date
Laszlo Nagy 93897b4cb5 jesd204_rx_static_config: Update to Np 12 interface changes 2021-02-05 15:24:15 +02:00
Laszlo Nagy 71475e7dd8 jesd204: Expose core synthesis parameters through registers
Make synthesis parameters accessible for the drivers.
Rework implementation to reflect the parameters of the actual core and
not of the AXI interfacing core.
2021-02-05 15:24:15 +02:00
Laszlo Nagy 454b900f90 jesd204: Xilinx: NP=12 support
To support deterministic latency with non-power of two octets per frame
(F=3,6) the interface width towards the transport layer must be resized
to match integer multiple of frames.

e.g  Input datapath width = 4; Output datpath width = 6;
  for F=3 one beat contains 2 frames
  for F=6 one beat contains 1 frame

The width change is realized with a gearbox.

Due the interface width change the single clock domain core is split
in two clock domains.
  - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b
  -              lane rate / 20 for input datapath width of 8 octets 8b10b
  -              lane rate / 66 for input datapath width of 8 octets 64b66b

  - Device clock : Link clock * input data path width / output datapath width

Interface to transport layer and SYSREF handling is moved to device clock domain.

The configuration interface reflects the dual clock domain.

If Input and Output datapath width matches, the gearbox is no longer
required, a single clock can be connected to both clocks.
2021-02-05 15:24:15 +02:00
Laszlo Nagy 6ef803e7ab jesd204: Make character replacement opt in feature
In order to keep resource utilization low and for better timing closure
allow disabling of the character replacement logic.

If the parameter is set the frame alignment monitoring is limited to links
where scrambling is on.
2021-02-05 15:24:15 +02:00
Matt Blanton 7093e10ebf jesd204: Fixed TX frame mark timing. Added start and end of multiframe signals as RX and TX ports 2021-02-05 15:24:15 +02:00
Matt Blanton 400c3927f7 jesd204: Add support for 8-byte JESD204B, frame alignment character insertion/replacement
Add support to JESD204 RX and TX core for 8-byte 8b/10b link mode,
and frame alignment character replace/insert with or without scrambling.
Add support for xcelium simulator to jesd204/tb
Increased cores minor version.
2021-02-05 15:24:15 +02:00
Laszlo Nagy 01f4576fcd ad_ip_jesd204_tpl_dac: added xbar for user channels (dma data)
Allow channels received from dma to re-map to other channels, e.g. allowing
broadcasting the same channel to all channels.

The feature is selectable with synthesis parameter and disabled by default.
2020-11-27 09:45:11 +02:00
Adrian Costina 7309da59d1 ad_ip_jesd204_tpl_dac: Switch to sync arm toggling instead of setting only
Added the second flip flop for timing reasons
2020-11-05 17:42:41 +02:00
Istvan Csomortani 0413bea5c1 ad_ip_jesd204_tpl: Extend valid attribute ranges 2020-10-26 18:12:14 +02:00
Istvan Csomortani 37254358dd makefile: Regenerate make files 2020-10-20 12:51:10 +03:00
Laszlo Nagy c3983d779c ad_ip_jesd204_tpl_adc: Fix PN check for twos complement data format
For devices which have twos complement as data format the MSB of the raw
input must not be toggled.
2020-10-13 12:55:17 +03:00
Josh Blum 6da4f61786 ad_ip_jesd204_tpl_dac_framer: fix localparam ordering
The parameters were not in the order of invocation and this causes an
error in the vivado simulator (xsim).
2020-10-10 08:27:00 +03:00
Laszlo Nagy e759c1855b jesd204: Clean-up combinatorial logic
To correctly model combinatorial logic in always blocks
blocking assignments must be used.
2020-09-29 17:27:42 +03:00
Laszlo Nagy 7c523fbf02 jesd204_rx: Reset frame alignment monitor event generator
If the link is not enabled no event should be generated.
2020-09-29 17:27:42 +03:00
Laszlo Nagy 0ecf4254ec axi_jesd204_rx: Ignore events if link not enabled
When the link is disabled the events can be ignored.
This is required by the free running event counter that can catch
invalid events during startup cased for example by an invalid link clock.
2020-09-29 17:27:42 +03:00
Laszlo Nagy aa4de79045 jesd204/jesd204_rx: Ignore frame alignment errors if lane is not in DATA phase
If the lane looses synchronization due invalid characters or disparity
error the lane alignment monitor checks random input which results in
irrelevant reporting of frame alignment error.
2020-09-29 17:27:42 +03:00
Laszlo Nagy d825fffd62 jesd204/jesd204_rx: Reset error counter once all lanes synced
If all lanes are synchronized (CGS state machine is in DATA phase) for long
enough therefore the link is also synchronized/DATA phase reset the error
counter since the accumulated values during INIT/CHECK are irrelevant.
These errors are handled by the per-lane CGS state machine.

All errors accumulated during INIT/CHECK phase of CGS are relevant only
if the link is unable to reach the DATA phase.
The link stays in DATA phase unless software resets it,
so all errors accumulated during the DATA phase are relevant.
2020-09-29 17:27:42 +03:00
Laszlo Nagy ee143d80d6 jesd204_rx/jesd204_rx_ctrl: Fix de-glitch mechanism
The previous implementation of the de-glitch only delayed the assertion
of the SYNC phase by 64 clock cycles with the DEGLITCH state but if meanwhile
one of the lanes got into a bad state cgs_ready de-asserted the state machine
continued to go SYNCHRONIZED (DATA) state.
This change extends the required number of consecutive cycles while all lanes
must stay in data phase before moving the link to SYNCHRONIZED state from 8 to 256;
This increases the reliability of link bring-up without needing extra
link restarts from software side.
2020-09-29 17:27:42 +03:00
Laszlo Nagy 5edc798b6b axi_jesd204_common/jesd204_up_common: Add event stats
Add statistics for :
 - number of link enable events
 - number of interrupt events (regardless of mask)

0x0B0 0x2C0 Stats Control Register
  [0] - Write 1 to clear stat registers

0x0B1 0x2C4 Link Enable Stat Register
  [15:0] Number of times the link was enabled from power-on or from last
         stat clear

0x0B4 0x2D0 IRQ Stat Register 0
  [31:16] IRQ 1 counter
  [15:0]  IRQ 0 counter

0x0B5 0x2D4 IRQ Stat Register 1
  [31:16] IRQ 3 counter
  [15:0]  IRQ 2 counter

0x0B6 0x2D8 IRQ Stat Register 2
  [31:16] IRQ 5 counter
  [15:0]  IRQ 4 counter

0x0B7 0x2DC IRQ Stat Register 3
  [31:16] IRQ 7 counter
  [15:0]  IRQ 6 counter
2020-09-29 17:27:42 +03:00
Istvan Csomortani 256593623c intel/adi_jesd204: Add an additional pipeline stage to RX soft PCS 2020-09-09 14:15:37 +03:00
Istvan Csomortani 72a4d54b76 jesd204_rx: Fix SDC constraint 2020-09-09 14:15:37 +03:00
Laszlo Nagy b49928fca6 ad_ip_jesd204_tpl_adc: add support for 64 channels 2020-08-11 10:37:59 +03:00
Laszlo Nagy 2ca09adaf7 ad_ip_jesd204_tpl_dac: expand address space to accomodate 64 channels 2020-08-11 10:37:59 +03:00
Laszlo Nagy e698b286e5 jesd204: DAC TPL to support 64 channels 2020-08-11 10:37:59 +03:00
Laszlo Nagy 6ca6257341 jesd204_rx: Increment version to 1.04.a
- support for frame alignment check
- support for interrupt on frame alignment error
- support for interrupt on unexpected lane status error
2020-07-31 11:43:41 +03:00
Laszlo Nagy 87b67ced17 jesd204_rx: Interrupt for unexpected lane status error 2020-07-31 11:43:41 +03:00
Laszlo Nagy 5e16eb85bb jesd204_rx: Generate interrupt on frame alignment error
When frame alignment error monitoring is enabled and error threshold is met
at least for one lane, generate an interrupt so software can reset the link and
do further bring-up steps.
2020-07-31 11:43:41 +03:00
Laszlo Nagy 15e14c76b9 jesd204_rx: Don't auto reset on frame alignment error by default
Let software handle the error case by default. Other steps might be
required to bring-up properly the link if one shot SYSREF is used.
2020-07-31 11:43:41 +03:00
Matt Blanton 1e04b2e2f2 jesd204_rx: Add RX frame alignment character check
Add support for RX frame alignment character checking when scrambling is enabled and
for link reset on misalignment.
Add support for xcelium simulator to jesd204/tb
2020-07-31 11:43:41 +03:00
Laszlo Nagy 2e5a4eb684 jesd204: update README to reflect rev C 2020-06-23 13:52:35 +03:00
Istvan Csomortani d4c393332a ad_ip_jesd204_tpl: TPL has and address space of 4KB 2020-05-25 11:55:40 +03:00
Laszlo Nagy bff8a9fafb scripts/jesd204.tcl: rename tpl core instance
Having the same name for dac and adc TPLs creates conflict in the
address segment naming having random names associated to the segments.
This causes difficulties during scripting of the project in test bench
mode.
2020-05-20 19:08:25 +03:00
Adrian Costina 10c9f7a70d ad_ip_jesd204_tpl_dac: Add option for an external synchronization pin
The external synchronization signal should be synchronous with the
dac clock. Synchronization will be done on the rising edge of the signal.
The control bit is self clearing. Status bit shows that the synchronization
is armed but the synchronization signal has not yet been received

Added EXT_SYNC parameter to be able to keep the dac_sync original
behavior
2020-05-13 10:09:43 +03:00
Adrian Costina 5d4c6701d9 ad_ip_jesd204_tpl_adc: Add external synchronization
The external synchronization signal should be synchronous with the
adc clock. Synchronization will be done on the rising edge of the signal.
The control bit is self clearing. Status bit shows that the synchronization
is armed but the synchronization signal has not yet been received. While
the synchronization mechanism is armed, the adc_rst output signal is set

The current format should allow for the SYSREF signal to be used as
synchronous capture start, but will need to be disabled before the
synchronization mechanism is armed
2020-05-13 10:09:43 +03:00
Laszlo Nagy 70d139af7f jesd204/ad_ip_jesd204_tpl_dac: Fix Intel dependencies
Even if the IQ rotation is disabled in the projects all modules has to be
added to the list of dependencies to avoid compilation errors.
2020-04-08 10:50:28 +03:00
Laszlo Nagy af060700b8 jesd204/ad_ip_jesd204_tpl_dac: add I/Q roation 2020-04-03 11:16:37 +03:00
Maxim 341221dc91
jesd204: Update jesd204_tx_lane.v
Removed decoder for tx_ready.
2020-04-01 10:29:40 +03:00
Laszlo Nagy 4e191e7ac2 ad_ip_jesd204_tpl_dac: fix GUI and FPGA info population 2020-03-10 18:33:29 +02:00
Laszlo Nagy 557a72e35e ad_ip_jesd204_tpl_adc: fix GUI and FPGA info population 2020-03-10 18:33:29 +02:00
Laszlo Nagy 1b0a47c101 jesd204_rx: fix critical warning for undriven input 2020-03-10 18:17:56 +02:00
Laszlo Nagy 9cce513645 jesd204/axi_jesd204_tx: Update version 2020-02-10 09:47:07 +02:00
Laszlo Nagy b8e1daa22b jesd204/axi_jesd204_rx: Update version 2020-02-10 09:47:07 +02:00
Laszlo Nagy 587a3c1a8d scripts/jesd204.tcl: Added 64b mode to Rx scripting 2020-02-10 09:47:07 +02:00
Laszlo Nagy 72186324f3 tb/loopback_64b_tb: Testbench for 64b mode
Data integrity check over a loopbacked link.
2020-02-10 09:47:07 +02:00
Laszlo Nagy bd9836886f jesd204_rx_static_config: Added 64b mode to Rx static config 2020-02-10 09:47:07 +02:00
Laszlo Nagy c3afbbc8a8 jesd204/interfaces: Added 64b mode Rx signals 2020-02-10 09:47:07 +02:00
Laszlo Nagy 7cad1f81d9 axi_jesd204_rx: Added 64b mode 2020-02-10 09:47:07 +02:00
Laszlo Nagy d1072847df jesd204_rx: 64b mode support for receive peripheral
Instantiate 64B/66B decoder based on synthesis parameter.
2020-02-10 09:47:07 +02:00
Laszlo Nagy 075f703443 jesd204_tx_static_config: Added 64b mode Tx static config 2020-02-10 09:47:07 +02:00
Laszlo Nagy e2d12a5b53 jesd204/scripts: Add 64b mode to Tx scripting 2020-02-10 09:47:07 +02:00