fixed critical warnings generated when the NUM_OF_CLK_MONS parameter
is set to 0 and the constraints written in up_clock_mon_constr.xdc
cannot be applied; removed up_clock_mon_constr.xdc from ip core.
When the link is disabled the events can be ignored.
This is required by the free running event counter that can catch
invalid events during startup cased for example by an invalid link clock.
If the lane looses synchronization due invalid characters or disparity
error the lane alignment monitor checks random input which results in
irrelevant reporting of frame alignment error.
If all lanes are synchronized (CGS state machine is in DATA phase) for long
enough therefore the link is also synchronized/DATA phase reset the error
counter since the accumulated values during INIT/CHECK are irrelevant.
These errors are handled by the per-lane CGS state machine.
All errors accumulated during INIT/CHECK phase of CGS are relevant only
if the link is unable to reach the DATA phase.
The link stays in DATA phase unless software resets it,
so all errors accumulated during the DATA phase are relevant.
The previous implementation of the de-glitch only delayed the assertion
of the SYNC phase by 64 clock cycles with the DEGLITCH state but if meanwhile
one of the lanes got into a bad state cgs_ready de-asserted the state machine
continued to go SYNCHRONIZED (DATA) state.
This change extends the required number of consecutive cycles while all lanes
must stay in data phase before moving the link to SYNCHRONIZED state from 8 to 256;
This increases the reliability of link bring-up without needing extra
link restarts from software side.
Add statistics for :
- number of link enable events
- number of interrupt events (regardless of mask)
0x0B0 0x2C0 Stats Control Register
[0] - Write 1 to clear stat registers
0x0B1 0x2C4 Link Enable Stat Register
[15:0] Number of times the link was enabled from power-on or from last
stat clear
0x0B4 0x2D0 IRQ Stat Register 0
[31:16] IRQ 1 counter
[15:0] IRQ 0 counter
0x0B5 0x2D4 IRQ Stat Register 1
[31:16] IRQ 3 counter
[15:0] IRQ 2 counter
0x0B6 0x2D8 IRQ Stat Register 2
[31:16] IRQ 5 counter
[15:0] IRQ 4 counter
0x0B7 0x2DC IRQ Stat Register 3
[31:16] IRQ 7 counter
[15:0] IRQ 6 counter
Quartus Standard 19.1 throw a critical warning for registers that have
different reset and initial power-up level.
Do not initialize those registers so we can get rid of the warning.
Define both AXI4 Memory Mapped and microprocessor interface for the
reigster map, then activate/deactive one of it in fucntion of the memory
interface type parameter.
Define the missing status_sync interface, which should be connected to
the offload.
Context switching with a parameter is not a good idea. The simulator
may evaluate both branch of the IF statement, even though the inactive
branch may not be valid.
Use if..generate to make the code more robust for both synthesizers and
simulators.
Converting from RGB to YCbCr takes one less stage than converting
from YCbCr to RGB color space.
Moving extra delay stage(5), of the sync signals to a particular
YCbCr to RGB color space conversion case.
Define INPUT_PIPELINE parameter, which can be used to activate the
REGISTER_INPUTS parameter of the PHY. This parameter will add an
additional register stage into the incoming parallel data stream.
It can be used to relax the timing margin between the PHY and Link modules.
This patch contains an initial effort to support the Stratix 10
architecture in our JESD204 framework.
Several instances were updated, doing simple context switching using the
DEVICE_FAMILY system parameter:
- xcvr_reset_control
- lane PLL (ATX PLL)
- link PLL (fPLL)
- native XCVR instance
Apart from the slightly different parameters of the instances above,
there were small differences at the reconfiguration Avalon_MM interface.
The link_pll_reset_control is required just for Arria10, so in case of
Stratix10 it isn't instantiated.
In Stratix 10 architecture there are several additional ports of the
xcvr_reset_control module that must be connected to the native XCVR
instance or tied to GND.
The following xcvr_reset_control ports were defined and connected to the
XCVR:
- rx|tx_analogreset_stat
- rx|tx_digitalreset_stat
- pll_select
If dac_valid is not a constant '1' it gets synchronized with the
dac_data_sync signal. This causes that dac_valid never asserts while
dac_data_sync is high, this way skipping the phase initialization.
ADRV9001 interfacing IP supports the following modes on Xilinx devices:
A B C D E F G H
CSSI__1-lane 1 32 80 80 2.5 SDR 8
CSSI__1-lane 1 32 160 80 5 DDR 4
CSSI__4-lane 4 8 80 80 10 SDR 2
CSSI__4-lane 4 8 160 80 20 DDR 1
LSSI__1-lane 1 32 983.04 491.52 30.72 DDR 4
LSSI__2-lane 2 16 983.04 491.52 61.44 DDR 2
Columns description:
A - SSI Modes
B - Data Lanes Per Channel
C - Serialization factor Per data lane
D - Max data lane rate(MHz)
E - Max Clock rate (MHz)
F - Max Sample Rate for I/Q (MHz)
G - Data Type
H - DDS Rate
CSSI - CMOS Source Synchronous Interface
LSSI - LVDS Source Synchronous Interface
Intel devices supports only CSSI modes.
De-assert dac_rst together with an updated control set.
This allows writing the control registers before releasing the reset.
This is important at start-up when stable set of controls is required.
De-assert adc_rst together with an updated control set.
This allows writing the control registers before releasing the reset.
This is important at start-up when stable set of controls is required.
Allow monitoring of non-PN patterns which have zeros in it.
e.g. nible-ramp, full range ramp.
Singular zeros got ignored if not out of sync, while OOS_THRESHOLD
consecutive zeros or non-matching data asserts the out of sync line.
Fix the *_ip.tcl scripts for axi_spi_engine and spi_engine_offload
module.
In case of a bool parameters the value_format and value properties must
be set for both user and hdl paramters. If not, in the generated verilog
code the tool will use "true" or "false" strings, instead of 0 or 1.
The input data path has a delay section that compensates for the ADC path delay.
By using a Dynamic Shift Registers coding style we can improve/change the
resource utilization on m2k:
Before After Resources
LUT 10097 10048 48 (0.28%)
LUTRAM 516 540 -24 (-0.4%)
FF 15285 14803 482 (1.37%)
The number of delay taps in the LA data path can be controlled manually, from
the regmap or automatically, according to the axi_adc_decimate's rate.
Moreover, because the rate is configure by software, and the time of
initialization, is different for the ADC path and LA path. There is an
uncertainty of plus/minus one sample between the two. Because ADC and LA
paths share the same clock we can easily synchronize the two paths. We
can't use reset, because the rate generation mechanism is different
between the two. So the ADC path is used as master valid generator and we
can use it to drive the LA path.
The synchronization is done by setting the rate source bit. This
mechanism can only be used if the desired rate for both path is equal,
including oversampling fom ADC decimation.
Adds information on:
- Log 2 of interface data widths in bits
- Interface type (0 - Axi MemoryMap, 1 - AXI Stream, 2 - FIFO ) .
Lets the driver discover interface widths and interface type settings,
this will deprecate the corresponding device tree properties.
This is useful in case of parametrized projects where the width of
the datapath is changing. This change will allow the use of a generic
device tree node.
Updated version to 4.3.a
Optimize the oversampling mechanism.
The behavior of the axi_dac_interpolate was changing if a debug module was
added to the core.
The current code has a better utilization and reliability.
When using an oversampling of 2 for axi_dac_interpolate the rate was
the same as with oversampling by 1(bypassing).
This commit removes the bypass for the ratio of 2.
For projects where the clock ratio between the sampling clock and core clock
is higher than 2, the ad_dds generates a number of samples equal with
the clock ratio. There is a phase offset between the samples, proportional
with the requested DDS frequency.
In scenarios where the DDS out frequency is closer to the upper
limit(Nyquist) and/or the clock ratio is also greater than 2 and the
dac_data_sync reminds low for an extended period of time, the DAC will
receive at each core clock period, a number of samples equal with the
clock ratio and with an amplitude influenced by the DDS out frequency.
In most cases similar with a sawtooth signal.
With this commit we ensures that samples received by the DAC are 0 for
the period where dac_data_sync signal is high. Only when the signal
transitions to low, the phase accumulator is initialized and the phase
information is passed to the phase to amplitude converter.
Another issue can appear when the sync signal is too short; less then
CLK_RATIO * clock cycles. Because the phase accumulator will not
synchronize at all stages, the final result will be a random combination of
sine-waves. Added a minimum sync pulse after the dac_data_sync is set
low.
When frame alignment error monitoring is enabled and error threshold is met
at least for one lane, generate an interrupt so software can reset the link and
do further bring-up steps.
Add support for RX frame alignment character checking when scrambling is enabled and
for link reset on misalignment.
Add support for xcelium simulator to jesd204/tb
The Pattern generator is part of the axi_logic_analyzer core.
The trigger signal can be internal (Oscilloscope or Logic Analyzer) or
external(TI or TO pins).
sergiu arpadi
Laszlo Nagy
Josh Blum
Istvan Csomortani
stefan.raus
AndreiGrozav
Stanca Pop
Rodrigo Alencar
Matt Blanton