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5127 Commits (94f8d1b4244e1527d263278041e7c06231e34488)

Author SHA1 Message Date
Istvan Csomortani 94f8d1b424 util_axis_upscale: Sign extension must be done separately for each channel 2019-06-28 11:18:29 +03:00
Istvan Csomortani 5f8269da03 spi_egine: Add a new register for dynamic transfer length configuration 2019-06-28 11:18:29 +03:00
Istvan Csomortani 40fbb37d6f spi_engine: Add additional synchronization FIFO's to axi_spi_engine 
Add additional synchronization FIFOs to several interfaces of the
axi_spi_engine module, to prevent metastability and timing issues in
case when the system clock and the SPI clock are asynchronous.
 2019-06-28 11:18:29 +03:00
Istvan Csomortani 91801bfe0d spi_engine: Update the ad_rst instance 2019-06-28 11:18:29 +03:00
Istvan Csomortani 68c1f92066 spi_engine: Add a CDC fifo for the SYNC interface too 2019-06-28 11:18:29 +03:00
Istvan Csomortani a19f6197cc spi_engine: Fix indentation of axi_spi_engine.v 2019-06-28 11:18:29 +03:00
Istvan Csomortani b81c8373e5 spi_engine: In read only mode SDO line should stay in its default level 2019-06-28 11:18:29 +03:00
Istvan Csomortani 85bbf95c57 spi_engine/offload: SDI_READY should be asserted while offload is inactive 2019-06-28 11:18:29 +03:00
Istvan Csomortani 746f457ef9 spi_engine: Software reset should reset the offload control registers too 2019-06-28 11:18:29 +03:00
Istvan Csomortani 19655b8092 spi_engine: Define SDO default state 
There are devices where the SDO default state, between transactions, is
not GND, rather VCC.

Define a parameter, which can be used to set the default state of the
SDO line.
 2019-06-28 11:18:29 +03:00
Istvan Csomortani 45a08a004d spi_engine:execution: Set default SDI driver value for all ports 2019-06-28 11:18:29 +03:00
Istvan Csomortani 8fb6fb329e util_dec256sinc24b: Fix the differentiator 
Move the subtraction outside of the always block. In this way we're not adding
an additional delay element on to the output of the differentiator,
which brakes the transfer function of the filter.
 2019-06-28 11:18:29 +03:00
Istvan Csomortani b46a28d42f adum7701: Delete redundant interrupt port in system_top 2019-06-28 11:18:29 +03:00
Istvan Csomortani a15afa6c03 util_dec256sinc24b: Avoid generated clock from logic 
Do not use word_clk, create a clock enable signal instead.
 2019-06-28 11:18:29 +03:00
Istvan Csomortani 59ce663479 util_dec256sinc24b: Fix resets 2019-06-28 11:18:29 +03:00
Istvan Csomortani 6668accc96 ad7405 : Initial commit 
This project is an inital version of the ADuM7701 (CMOS) or AD7405 (LVDS)
reference board.
 2019-06-28 11:18:29 +03:00
Istvan Csomortani 554feaa1af util_pulse_gen: Update ports for all outdated instance 
The new version of util_pulse_gen has different ports and port names.

Update all the instance:
  - AD738x_FMC
  - AD7768EVB
  - ADAQ7980_SDZ
 2019-06-28 11:18:29 +03:00
Istvan Csomortani 7fa620d253 gtm_projects: Update system_top 
In the latest system_top file we are not bringing out all the interrupt
signals from the block design. Delete all interrupt ports from the
system_wrapper instance.

Following projects were changed:

  - AD5766_SDZ
  - AD7134_FMC
  - AD7616_SDZ
  - AD77681EVB
  - AD7768EVB
  - ADAQ7980
 2019-06-28 11:18:29 +03:00
Istvan Csomortani 21ce53f765 Revert "Move GTM projects to gtm_projects branch" 
This reverts commit 171093eca4.
 2019-06-28 11:18:29 +03:00
Istvan Csomortani f22f448d4b daq3:vcu118: Delete constraint related to smart connect 
Apparently this constraint will cause more harm than good. The tool will
try to prevent an invalid hold violation by increasing the net delay,
causing a setup violation on the same path. (inside the smart connect)

See more info here:
https://forums.xilinx.com/t5/AXI-Infrastructure/Smartconnect-and-Synchronous-Clock-Domain-Crossing-Issues/td-p/904824
 2019-06-27 13:47:24 +03:00
Istvan Csomortani 65fea6c4c0 ad_ip_jesd204_tpl_dac: Fix up_axi instantiation 
This patch will fix the following warning:

[Synth 8-689] width (16) of port connection 'up_axi_awaddr'
does not match port width (12) of module 'up_axi'
 2019-06-27 13:47:00 +03:00
Laszlo Nagy acf6d618dd util_clkdiv: fix for multiple instances 
Vivado propagates and auto derives the clocks, however if multiple
instances of this components are used the names of the propagated clock
change while the constraint file has fixed name which will match only
the clocks from the first instance letting the second instance of the
clock div without exception.
 2019-06-27 10:33:51 +03:00
Laszlo Nagy fd6a395347 axi_fmcadc5_sync: rename generated spi clock 
Rename the clock so it won't conflict with the main spi clock name.
 2019-06-26 16:10:07 +03:00
AndreiGrozav 1c99fde06b axi_ad9361: Fix Intel interface - technology encoding update 2019-06-25 15:40:51 +03:00
AndreiGrozav 01081c93e8 axi_ad9361: Fix the interface for Intel devices 
Use missing MIMO_ENABLE parameter, which will insert
and additional de-skew logic to prevent timing issues coming from
the clock skew differences of two or multiple AD9361.
 2019-06-25 15:40:51 +03:00
Adrian Costina 81bcf9f6fc util_adxcvr: Cleanup whitespaces for GTY4 instantiations 2019-06-25 15:35:49 +03:00
Istvan Csomortani 4896a84c2d ad9739a_fmc: DMA should use $sys_dma_resetn 2019-06-21 09:54:21 +03:00
Istvan Csomortani e0a010c959 ad9625_fmc: DMA should use $sys_dma_resetn 2019-06-21 09:54:21 +03:00
AndreiGrozav 4812f64cdc ad9434: Fix axi_ad9434_dma timing closure 
axi_ad9434_dma/m_dest_axi_aresetn should use sys_dma_resetn
 2019-06-21 09:54:21 +03:00
AndreiGrozav 0a3a99bf83 m2k: Define SPI clock constraint 2019-06-21 09:53:14 +03:00
Sergiu Arpadi 0bbe501764 adrv9009_zu11eg_som: added axi_fan_control 2019-06-14 17:08:38 +03:00
Sergiu Arpadi c159909823 adrv9009_zu11eg_som: added i2s 2019-06-14 17:08:38 +03:00
Adrian Costina 9409df6a6f adrv9009_zu11eg: Initial commit 
Observation and RX should never run at the same time.
Given that there is no FIFO on the RX and OBS paths, they will use the higheste performance HP ports, which are HP1 and HP2
 2019-06-14 17:08:38 +03:00
Sergiu Arpadi 369974f2e7 axi_fan_control: updated ip 
fixed tacho evaluation bug; updated fsm;
 2019-06-14 17:08:38 +03:00
Istvan Csomortani 95afc461a6 fmcomms5: DMA should use $sys_dma_resetn 2019-06-13 10:59:43 +03:00
Istvan Csomortani 2e05b70d94 fmcomms11: DMA should use $sys_dma_resetn 2019-06-13 10:59:43 +03:00
Istvan Csomortani dafc97f43a fmcjesdadc1: DMA should use $sys_dma_resetn 2019-06-13 10:59:43 +03:00
Istvan Csomortani 424abe0c02 adrv9009: DMA should use $sys_dma_resetn 2019-06-13 10:59:43 +03:00
Istvan Csomortani 5266d2ae88 ad6676evb: DMA should use $sys_dma_resetn 2019-06-13 10:59:43 +03:00
Istvan Csomortani 92a0e8eb1e util_adcfifo: Fix SDC cosntraints 2019-06-13 10:59:43 +03:00
Istvan Csomortani 78b14f9803 axi_ad9625: Fix the interface instance 
The axi_ad9625_if does not have a DELAY_REFCLK_FREQUENCY parameter.
 2019-06-13 10:59:43 +03:00
Istvan Csomortani 44a9331471 fmcomms2:fmcomms5: ZCU102 uses 500MHz IO delay clock 2019-06-11 18:13:06 +03:00
Istvan Csomortani 20b0c92a1f iodelay: Expose the REFCLK_FREQUENCY parameter 2019-06-11 18:13:06 +03:00
Istvan Csomortani 993497438b adi_project:adi_project_run: Check if $num_reg exist 2019-06-11 18:13:06 +03:00
Istvan Csomortani 896ea4925d adi_board: Fix ad_mem_hpx_interconnect proc 
Make the lsearch command more robust.
 2019-06-11 18:13:06 +03:00
Istvan Csomortani 019390f9bf block_design: Updates with new reset net variables 2019-06-11 18:13:06 +03:00
Istvan Csomortani 0e750bea42 adrv9009: Fix dma_clk tree 2019-06-11 18:13:06 +03:00
Istvan Csomortani 9072779e41 adrv9371x: Clean out system_db.tcl 2019-06-11 18:13:06 +03:00
Istvan Csomortani de510b45ab base: Add system_processor_rst for all the global clocks 2019-06-11 18:13:06 +03:00
Istvan Csomortani 7960b00684 block_design: Update with new clock net variables 
Using the new clock net variables in all Xilinx block designs.
 2019-06-11 18:13:06 +03:00