3 Commits (950acaed1500edc8582b8e52b3acda515b6bb9ce)

Author	SHA1	Message	Date
Rejeesh Kutty	ce1fed1ce6	dmafifo- adc/dac split	2016-08-16 12:54:39 -04:00
Istvan Csomortani	bb185296d7	fmcadc2_vc707: Increase the BRAM FIFO size to its maximum: it can store 1M samples. ... The 2^18 dma address width with a 64 dma data width will result a FIFO, what will be implemented by 512 RAMB36 cells. This is a the maximum BRAM FIFO depth in case of the VC707.	2015-04-23 18:00:00 +03:00
Rejeesh Kutty	19e4950b72	renamed to match official names	2014-12-08 10:44:15 -05:00