zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
3,263 Commits
1 Branch
0 Tags
23 MiB
Commit Graph

3263 Commits (95a2e02800381de8a43e2121f8e5ed292143017a)

Author SHA1 Message Date
AndreiGrozav b3ed38107c axi_i2s_adi: changed adi_ip_properties lite to adi_ip_properties, so that the axi interface can be inferred 2016-03-15 10:12:45 +02:00
Rejeesh Kutty 8ecf5edaf8 ad9122- pat modes 2016-03-14 11:14:29 -04:00
AndreiGrozav 31cc91d1b9 adi_ip: Updated to 2014.4.2 
- automatically infer clocks, resets, axim_mm and axis interfaces
 2016-03-14 15:14:18 +02:00
Adrian Costina 33b265a742 Makefile: Update Makefiles 2016-03-14 09:31:17 +02:00
Rejeesh Kutty 561412e322 pzsdr-cmos swap 2016-03-11 11:25:58 -05:00
Rejeesh Kutty c7ee15d4f4 ccbrk_cmos: cmos mode 2016-03-11 11:25:58 -05:00
Rejeesh Kutty c566784ba9 ccbrk_cmos: ccbrk copy 2016-03-11 11:25:58 -05:00
Istvan Csomortani 573146aa96 axi_ad7616: Fix the data width of the AXI stream interface 2016-03-10 16:38:53 +02:00
Lars-Peter Clausen 287770a201 axi_dmac: Fix tlast generation on AXI stream master 
For the AXI stream interface we want to generate TLAST only at the end of
the transfer, rather than at the end of each burst.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2016-03-08 10:53:59 +01:00
Adrian Costina 2524f19ae0 Updated interfaces Makefile and Makefiles for the libraries that depend on it 2016-03-07 12:31:41 +02:00
Istvan Csomortani b0f90bd0e8 daq1/cpld: Read interface fix 2016-03-04 20:28:24 +02:00
Istvan Csomortani 7e607957ee daq1.cpld: Prevent the spi_counter to roll over. 2016-03-04 20:28:22 +02:00
Istvan Csomortani 262a42c676 daq1/cpld: Update CPLD_VERSION value 2016-03-04 20:28:20 +02:00
Istvan Csomortani 9439862301 daq1/cpld: Update CPLD 
Change to control line fpga_to_cpld to cpld_to_fpga, this is not a functional change.
 2016-03-04 20:28:18 +02:00
Rejeesh Kutty 583ef82fd0 ad9361- cmos mode 2016-03-04 10:39:48 -05:00
Rejeesh Kutty 7a320a3d34 ad_lvds* - updates 2016-03-04 10:39:48 -05:00
Rejeesh Kutty 3466f21f8e pzsdr add cmos/lvds support 2016-03-04 10:39:48 -05:00
Rejeesh Kutty 18f30c8dc8 pzsdr- cmos/lvds split 2016-03-04 10:39:48 -05:00
Rejeesh Kutty a2374f64bf pzsdr- cmos/lvds split 2016-03-04 10:39:48 -05:00
Rejeesh Kutty 7d2939be92 ad9361- cmos mode initial commit 2016-03-04 10:39:48 -05:00
Adrian Costina 977d9d0624 Merge branch 'hdl_2015_r2' into dev 
Conflicts:
	projects/daq1/common/daq1_spi.v
 2016-03-02 13:52:15 +02:00
Adrian Costina 40fb68dfd5 ad9265, ad9434, ad9467, daq1, daq2, daq3, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1, fmcomms6, fmcomms7, usdrx1: updated common spi module so that spi streaming is possible 2016-03-02 13:39:37 +02:00
Adrian Costina becc23a69b daq2: Modified common spi module so that spi streaming is possible 
- stop incrementing spi_count after the instruction cycle
 2016-03-01 17:25:58 +02:00
Rejeesh Kutty f7e490c2b3 hdlmake.pl updates 2016-02-26 13:46:11 -05:00
Rejeesh Kutty e012d0519b Merge remote-tracking branch 'origin/hdl_2015_r2' into dev 2016-02-26 13:39:39 -05:00
Rejeesh Kutty f6e64e42b0 kcu105: add ethernet idelaycntrl 2016-02-26 13:19:49 -05:00
Istvan Csomortani 59313f3c90 daq1: ADC DMA must be in none-cyclic mode 2016-02-24 14:37:19 +02:00
Istvan Csomortani c0a559a9b1 daq1: Fix some typos in the SPI wrapper 2016-02-24 14:31:56 +02:00
Adrian Costina 8ccd8d87bb daq2: A10GX, increase analog/digital reset durations 
- reset the xcvr_rst_cntrl only from the axi_jesd_xcvr
- checked separate RX/TX reset per channel
 2016-02-23 11:41:38 +02:00
Adrian Costina 89f7aadfb1 fmcjesdadc1: A5GT, connected xcvr_rxt_cntrl reset input to the axi_jesd_xcvr reset output 
This will allow for the transceivers to be reset by the axi_jesd_xcvr core
 2016-02-23 11:31:07 +02:00
Rejeesh Kutty 4fb6589b2d pzsdr/ccfmc: add fan controls 2016-02-19 16:40:54 -05:00
Adrian Costina 377461e0d4 Merge branch 'hdl_2015_r2' into dev 2016-02-19 14:15:27 +02:00
Adrian Costina 0f37dd6424 fmcjesdadc1: Fixed project 
- changed system_project.tcl so that all base designs to be included
- changed DMA properties to take into consideration the new parameter names
- changed reset bridges to asynchronous
- increased maximum burst size of the DMA bridge
- changed the data_width of the memory bus to 256, as with 512 timing violations may occur
- changed base addresses for the base system to be the same as in the previous release
 2016-02-19 14:09:57 +02:00
Rejeesh Kutty ce760eb691 fmcadc2- add adf4355 access 2016-02-18 16:17:33 -05:00
Rejeesh Kutty a8e9d72273 adc/dac - prefix parameters 2016-02-17 14:16:04 -05:00
Adrian Costina d94f157454 arradio: Changed ADC/DAC DMA address length to 24 bit 2016-02-16 15:27:51 +02:00
Adrian Costina 43e03ca6f7 arradio: Updated project 
- made the reset bridges asynchronous
- connected the arradio gpio to the CPU interconnect
 2016-02-16 14:50:23 +02:00
Istvan Csomortani 5518c47ca4 daq1_cpld: Set Input and tristate I/O termination mode to FLOAT 2016-02-15 19:27:59 +02:00
Istvan Csomortani 051ac307e6 daq1_cpld: Do not forward the first eight clock cycles of fmc_spi_sclk to sclk 2016-02-15 19:26:58 +02:00
Istvan Csomortani 9370246cfa daq1: Fix bugs on CPLD design 
Fix the CSN forwarding.
 2016-02-12 16:59:09 +02:00
Istvan Csomortani 5ed2c0b599 daq1: Update CPLD constraints file 2016-02-12 16:54:36 +02:00
Istvan Csomortani aa2ff0223a daq1: Update CPLD design 
+ SPI counter counts on negative edge of the SPI_CLK
+ Shift register for read, shifting MSB first
+ Fix write access logic
+ Update the internal register addresses
 2016-02-12 14:45:18 +02:00
Istvan Csomortani e1c5d6a8f7 axi_ad9684: Fix constraint file 2016-02-12 14:38:59 +02:00
Istvan Csomortani c32d7147d5 daq1 : There is a single CSN from master 2016-02-12 14:38:32 +02:00
Istvan Csomortani 9675df15c6 daq1_zc706: Update constraints file 2016-02-12 14:37:02 +02:00
Istvan Csomortani a747fad540 axi_ad9361: tx_valid must be controlled by the TDD controller 2016-02-12 14:33:34 +02:00
Istvan Csomortani e381d5170c util_tdd_sync: Update the synchronization interface 
Simplify the synchronization interface, there is one signal line between the synchronization module and transceiver core.
 2016-02-12 14:27:37 +02:00
Istvan Csomortani 1c3795ad02 Update .gitattributes 
Add xise file extension to .gitattributes
 2016-02-12 14:27:35 +02:00
Adrian Costina 61f9f72a75 fmcjesdadc1: Updated VC707 project for maximum throughput from DMA to DDR 
- Increased the DMAs internal FIFO
 2016-02-09 12:30:56 +02:00
Adrian Costina c431adb793 fmcjesdadc1: Updated KC705 project for maximum throughput from DMA to DDR 
- Increased the DMA internal FIFO
 2016-02-09 12:00:27 +02:00