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2 Commits (96c81013acb65e5b0969cd2ac361e4c0b472c84a)

Author SHA1 Message Date
Istvan Csomortani 19732d89fb plddr3: Fix the adc_dwr pulse width 
The adc_dwr signal pulse width was to long, need to be just one adc_clk cycle.
 2014-12-09 13:51:00 +02:00
Rejeesh Kutty 81b4cd532d axi_fifo2s: include bus width/clock transfer 2014-11-12 14:43:38 -05:00