Commit Graph

17 Commits (98d3d44fd1247eae1ef460734ece3a0028d91d37)

Author SHA1 Message Date
Lars-Peter Clausen fa9d94bfe8 avl_adxcvr: Perform octet order swap
The ADI transport layer peripherals expect the first octet to be in the
LSBs and the last octet to be in the MSBs. The Altera JESD204 core orders
the octets the other way around though, first octet in the MSBs and last
octet in the LSBS.

Currently this is handled by having each transport layer peripheral swap
the octets around when it is connected to the Altera JESD204 core.

Change this so that rather than having to do the data swizzling in every in
every transport layer peripheral perform it at the input/output of the link
layer peripheral inside the generated block.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-03 17:57:58 +02:00
Lars-Peter Clausen 69a23ecde3 avl_adxcvr: Simplify TX lane mapping
Currently the TX lane mapping is implemented by having to connect tx_phy_s_* to
the tx_ip_s_* and the tx_phy_d_* to the tx_ip_d_* signals in the system
qsys file in the desired order.

Re-work things so that instead the lane mapping is provided through the
TX_LANE_MAP parameter. The parameter specifies in which order logical lanes
are mapped onto the physical lanes.

The appropriate connections are than made inside the core according to this
parameter rather than having to manually connect the signals externally.

In order to generate a 1-to-1 mapping the TX_LANE_MAP parameter can be left
empty.

This change slightly reduces the boiler-plate code that is necessary to
setup the transceiver.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-03 17:57:58 +02:00
Lars-Peter Clausen d7e87a60a9 Remove executable flag from non-executable files
All of these files are source code and are not executable standalone.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-28 17:56:07 +02:00
Lars-Peter Clausen f0655e63a6 avl_adxcvr: Derive PLL and core clock frequency from lane rate
The PLL frequency must be half of the lane rate and the core clock rate
must be lane rate divided by 40. There is no other option, otherwise things
wont work.

Instead of having to manually specify PLL and core clock frequency derive
them in the transceiver script. This reduces the risk of accidental
misconfiguration.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-28 15:11:08 +02:00
Lars-Peter Clausen a0f4adabd0 avl_adxcvr: Fix core clock bridge frequency
The clock bridge expects the clock rate to be specified in Hz, but
$m_coreclk_frequency is in MHz. Do the appropriate conversion.

Nothing seems to rely on the clock bridge reporting the correct frequency
at the moment, so this is only a cosmetic change.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-28 15:11:08 +02:00
Rejeesh Kutty 354b311f3d library/avl_adxcvr: fpll fixes 2017-06-21 15:26:00 -04:00
Rejeesh Kutty 9464f342cf avl_adxcvr: remove arria v support 2017-06-15 11:36:14 -04:00
Rejeesh Kutty 173837f5b2 altera- altera ip interfaces has no consistency 2017-06-09 16:21:44 -04:00
Rejeesh Kutty 034aa7c1ee altera 16.1- recommends using fpll for dedicated low skew clock routing 2017-06-08 10:50:52 -04:00
Rejeesh Kutty ebeebdddf0 altera- infer latest versions 2017-05-12 13:40:14 -04:00
Rejeesh Kutty c728299e71 altera- default to latest version 2017-05-12 13:25:17 -04:00
Rejeesh Kutty 0b58a2a1db avl_adxcvr- sysclk frequency 2016-11-09 09:21:07 -05:00
Rejeesh Kutty 48ee720901 avl_adxcvr- a5 requires single transceiver controller 2016-11-08 15:20:01 -05:00
Rejeesh Kutty ee9c8b884d avlxcvr- add arria v support 2016-11-04 15:01:19 -04:00
Rejeesh Kutty 21545ee83f avl_adxcvr- ip/phy split 2016-09-12 14:57:50 -04:00
Rejeesh Kutty 4ae084ee32 avl_adxcvr- compile fixes 2016-09-01 10:06:28 -04:00
Rejeesh Kutty b7ea2efa87 altera- xcvr cores 2016-08-29 15:18:48 -04:00