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Author SHA1 Message Date
AndreiGrozav 66823682b6 Add FPGA info parameters flow 
Common basic steps:
- Include/create infrastructure:

   * Intel:
       - require quartus::device package
       - set_module_property VALIDATION_CALLBACK info_param_validate

   * Xilinx
       - add bd.tcl, containing init{} procedure. The init procedure will be
         called when the IP will be instantiated into the block design.
       - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl
       - create GUI files

- add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params)
- add/propagate the info parameters through the IP verilog files

axi_clkgen
util_adxcvr
ad_ip_jesd204_tpl_adc
ad_ip_jesd204_tpl_dac
axi_ad5766
axi_ad6676
axi_ad9122
axi_ad9144
axi_ad9152
axi_ad9162
axi_ad9250
axi_ad9265
axi_ad9680
axi_ad9361
axi_ad9371
axi_adrv9009
axi_ad9739a
axi_ad9434
axi_ad9467
axi_ad9684
axi_ad9963
axi_ad9625
axi_ad9671
axi_hdmi_tx
axi_fmcadc5_sync
 2019-03-30 11:26:11 +02:00
AndreiGrozav 8a306ce96b axi_ad9162: Updates for ad_dds phase acc wrapper 2018-07-18 18:19:30 +03:00
AndreiGrozav 8dd1687094 axi_ad9162: Update for CORDIC algorithm 
Add the new files to the IP list
Propagate DDS parameters to top file
 2018-07-18 18:19:30 +03:00
Lars-Peter Clausen bd251a5fd5 Remove unused DMA overflow signal from DAC DMA interfaces 
The DAC DMA will never overflow and unsurprisingly the dac_dovf signal is
never used anywhere. It is very unlikely it will ever be used, so remove
it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2018-05-02 17:21:20 +02:00
Lars-Peter Clausen 8e90d5db20 axi_ad9162: Infer clock signal for tx_clk port 
Fixes the following warning:
  [BD 41-1731] Type mismatch between connected pins: /util_fmcomms11_xcvr/tx_out_clk_0(clk) and /axi_ad9162_core/tx_clk(undef)

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2018-04-18 15:16:13 +02:00
Istvan Csomortani c1bdfca4c3 library: Delete all adi_ip_constraint process call 2017-04-06 12:36:47 +03:00
Istvan Csomortani 873fbfd6d7 library: Update scripts with new constraints 
Update all IPs tcl scripts with the new constraints files.
Refer to commit 335fef0.
 2017-03-30 16:16:02 +03:00
Rejeesh Kutty c98e2e95dd ad9162- xcvr updates 2016-09-26 15:21:45 -04:00
Istvan Csomortani df36902713 lib_refactoring: Fix path of the IO macros 2016-08-08 15:07:19 +03:00
Shrutika Redkar d931b2ee64 ad9162 core verilog files 2016-06-30 10:24:01 -04:00