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6 Commits (99f9a75dfb0849f156c192df99ac15f33fce4e50)

Author SHA1 Message Date
Istvan Csomortani 9934cce5d2 util_dacfifo: Add CDC logic for dma_lastaddr register. 2015-05-11 12:20:46 +03:00
Istvan Csomortani a7c96fdac8 util_dacfifo: General clean up of the IO, input/output data has the same width 2015-05-06 16:32:44 +03:00
Istvan Csomortani 9fba4cb2ef util_dacfifo: Add support for Slave AXI stream interface. 
The FIFO can be initialized through an AXI stream interface too.
 2015-04-27 10:40:55 +03:00
Istvan Csomortani a100ecd308 util_dacfifo: Update BRAM DAC Fifo 
The fifo will be placed between the DMAC and the Upack module, all the interfaces were updated.
 2015-04-21 15:45:56 +03:00
Istvan Csomortani b7d8e38c94 util_dacfifo: General update 
+ Clean out the code, delete unnecessary flops
+ Add support for channel count (C_CH_CNT)
+ FIFO write (data from DMAC/upack) : valid just when xfer_req is asserted, address is free running, new xfer_req resets the address
+ FIFO read (data to DAC) : free running, reads to max address
 2015-04-09 11:43:37 +03:00
Rejeesh Kutty 056d6bbf40 dacfifo: added 2015-04-07 15:55:29 -04:00