Laszlo Nagy
889447e900
axi_ad9361: make IODELAYCTRL insertion optional
2022-01-25 09:50:31 +02:00
Laszlo Nagy
bc8e7881f2
axi_dmac: Hook up ID
...
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2022-01-25 09:50:22 +02:00
Iulia Moldovan
f3cf7508c8
ad9783: Update Makefile
2022-01-20 12:31:57 +02:00
LIacob106
9d94f21d89
scripts/adi_xilinx_device_info_enc.tcl: Change regex for vcu128
...
The regex does not match vcu128 as Ultrascale+. It matches for Ultrascale.
2022-01-12 17:32:47 +02:00
Filip Gherman
9d8097389c
library/jesd204/jesd204_common/pipeline_stage.v: Initialize pipeline stage register
2022-01-12 13:43:20 +02:00
Filip Gherman
080925e8fe
library/jesd204: tpl timing bug fix
2022-01-12 10:14:55 +02:00
Iulia Moldovan
08f029c757
axi_ad9783: Initial commit
2022-01-07 14:04:08 +02:00
David Winter
fcd3bfd349
util_pulse_gen: Reload registers when counter is at one
...
This patch fixes an issue where the pulse width is only updated two
periods after the current one.
Signed-off-by: David Winter <david.winter@analog.com>
2022-01-04 15:02:05 +02:00
AndreiGrozav
c2d960e029
axi_adrv9001: Add external sync support
...
The external sync must be synchronous to the reference clock, in order
to obtain a deterministic synchronization of the interface.
2021-12-16 15:16:30 +02:00
Laszlo Nagy
41525f348b
axi_adrv9001/axi_adrv9001_core.v: Disable TDD and IOCTRL if second SSI interface is disabled
2021-12-08 17:31:53 +02:00
Laszlo Nagy
dfe153dc68
axi_adrv9001/axi_adrv9001_tdd.v: Add disable option for TDD
2021-12-08 17:31:53 +02:00
Laszlo Nagy
8cc0367e8f
axi_adrv9001: Hide disabled interfaces
...
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-12-08 17:31:53 +02:00
Laszlo Nagy
6a4b46ebb4
axi_adrv9001: Make Rx2 and Tx2 source synchronous interfaces optional
...
If the Rx2 and Tx2 SSI are disabled the rx1,tx2 data paths are forced to
R1 mode.
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-12-08 17:31:53 +02:00
sergiu arpadi
c1ca578343
axi_ad7616: Fix sync port
2021-11-22 15:22:16 +02:00
Laszlo Nagy
8e0a45dea9
jesd204_rx/jesd204_lane_latency_monitor.v: Fix for datapath width of 4
...
Current implementation is correct only for datapath width of 8.
The buswidth of latency measurement inside a beat has a fixed width (3 bits)
for each lane that must be taken in account when computing the total latency.
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-11-19 18:14:43 +02:00
Laszlo Nagy
7e5a638386
jesd204_versal_gt_adapter_rx/tx: Infer Versal GT interface
2021-11-19 14:01:48 +02:00
Laszlo Nagy
b25c37a8cc
axi_adrv9001/intel: Add dummy parameters to match Xilinx interface
...
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-11-12 14:09:14 +02:00
Laszlo Nagy
36d0a8b3e8
library:util_pad: Initial version
...
Data to DMA/system memory must be presented in widths of multiple of 8 bits,
however this padding is not optimal if is done in the transport layer
since this will affect the DAC/ADC FIFO or offload storage.
This utility block adds or removes padding from sample stream in case the
sample with is not multiple of 8 bits, and can be placed between the DMA
and FIFO/Offload blocks.
2021-11-10 14:03:34 +02:00
Laszlo Nagy
cb8cf4b3d2
jesd204/scripts: Helper procedure for TPL width calculation
2021-11-10 14:03:34 +02:00
Laszlo Nagy
5dd9fd4832
axi_dmac: Allow wider FIFO/AXI Stream interface
...
On large projects with multiple channels the databus on the FIFO/AXI
stream interface can get wider that 1024 bits.
This commit allows a wider range for all the interfaces,
in case for the memory mapped interfaces where the range is 32-1024 the
user selects a bus width out of range that will be handled by the IPI.
2021-11-10 14:03:34 +02:00
Laszlo Nagy
fcb16daf5b
axi_adrv9001: Add the option of global clock buffers on 7 series
...
Using global clock can help placement issues where the logic does not fits in one
clock region.
2021-11-08 13:53:51 +02:00
Laszlo Nagy
7112fbce7e
library/scripts/adi_xilinx_device_info_enc.tcl: Add K26 support
2021-11-08 09:23:02 +02:00
Nicola Corna
5d7f4672f5
axi_i2s_adi: initialize cdc_sync_stage0_tick bits to '0'
2021-11-08 08:52:01 +02:00
Nicola Corna
18ab43b5a1
axi_hdmi_tx: Add UltraScale+ architecture to Verilog
2021-11-08 08:52:01 +02:00
Dan Hotoleanu
a381fe3e92
ad_ip_jesd204_tpl_adc: Add value of 14 to CONVERTER_RESOLUTION parameter
...
Added new allowed value of 14 for the CONVERTER_RESOLUTION parameter.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-11-04 12:18:06 +02:00
stefan.raus
3c07861ee8
generate_xml.sh: Replace < and > in error message
...
Replace < with < and > with > in ERRS to not broke created xml.
Signed-off-by: stefan.raus <stefan.raus@analog.com>
2021-11-03 15:22:45 +02:00
Laszlo Nagy
70cc53bbc8
ad_ip_jesd204_tpl_dac: Move external dac sync bit
2021-10-27 18:36:47 +03:00
Laszlo Nagy
7b0922e4dc
library/common/up_adc_common.v: Remove tabs
2021-10-27 18:36:47 +03:00
Laszlo Nagy
a9c9636780
library/common/up_dac_common.v: Cleanup spaces
2021-10-27 18:36:47 +03:00
Filip Gherman
9b7c2852b6
adxcvr: Increase version to 17.5.a
...
Add suport for XCVR phase adjust buffer status:
- Expose TXBUFSTATUS and RXBUFSTATUS
- Create RXBUFSTATUS_RST flag for clearing RXBUFSTATUS
2021-10-27 14:40:50 +03:00
Laszlo Nagy
d493b724f2
axi_adrv9001/adrv9001_rx.v: Simplify clocking
2021-10-27 14:40:08 +03:00
David Winter
6a5d2f76d5
data_offload: Fix oversized TX input transactions
...
Signed-off-by: David Winter <david.winter@analog.com>
2021-10-27 14:26:22 +03:00
David Winter
cd6024b341
Revert "data_offload: Fix oversized inputs in TX mode"
...
This reverts commit 0e8f55b2d7
.
2021-10-27 14:26:22 +03:00
sergiu arpadi
52df3c4937
ad463x_data_capture: Remove tb
2021-10-26 15:58:54 +03:00
LIacob106
076e81a17c
library: Add link to wiki for IPs
2021-10-25 10:44:53 +03:00
Istvan Csomortani
6a526f4bb6
ad463x_data_capture: Initial commit
...
IP required to support echo and master clock mode
2021-10-18 16:13:31 +03:00
Istvan Csomortani
5ac64b021f
spi_engine_execution: Delete control loop-back in sdi_data_valid generation
2021-10-18 16:13:31 +03:00
sergiu arpadi
6570c23a76
axi_spi_engine: Add generic config params
...
The 4 parameters are added to facilitate transmiting project
related information to the software. They act as read-only
memory which is written in Vivado when the project builds.
Set 31 to SDI FIFO's almost full threshold
2021-10-18 16:13:31 +03:00
Istvan Csomortani
f86ae28e50
spi_engine/data_reorder: Initial commit
...
In case of multiple SDI (MISO) lanes, the samples arrives in a parallel
fashion. For example in case of 4 MISO line, at the first latching clock
edge 4 bits of a sample will be saved, one bit into each shift register.
The data reorder module reconstruct the incoming samples from the AXI
stream of the offload module.
2021-10-18 16:13:31 +03:00
Istvan Csomortani
6565c5d018
library/tb: Improve run_tb.sh
2021-10-18 16:13:31 +03:00
LIacob106
e34346360d
scripts: Add logic for vivado version check
2021-10-12 14:34:11 +03:00
Laszlo Nagy
812baf9022
Revert "data_offload: Fix timing violation"
...
This reverts commit 1fe0d5f8e0
.
2021-10-08 11:42:05 +03:00
Filip Gherman
dbd5ffe4ed
jesd204_rx: fixed makefile
2021-10-07 12:48:08 +03:00
Laszlo Nagy
0c6c28ed84
jesd204/ad_ip_jesd204_tpl : Add support for 12 lanes
2021-10-06 15:49:56 +03:00
Laszlo Nagy
51b643b978
Makefile: Fix misc makefiles from projects and library
2021-10-05 14:24:48 +03:00
Laszlo Nagy
22e1366bfc
jesd204/jesd204_rx: Define tie off values for unused ports
2021-10-05 14:09:51 +03:00
Laszlo Nagy
aa93c17cdc
jesd204/jesd204_tx/jesd204_tx.v: Have FFs initial value, useful for simulation
2021-10-05 14:09:51 +03:00
Laszlo Nagy
1a9e7dbeb4
jesd204:jesd204_versal_gt_adapter_rx/tx: Add adapter for Versal transceiver IP
2021-10-05 14:09:51 +03:00
Laszlo Nagy
4d12c4d99a
scripts/adi_xilinx_device_info_enc.tcl: Add Versal support
2021-10-05 14:09:51 +03:00
Laszlo Nagy
2b242bf06f
scripts/adi_ip_xilinx.tcl: Enable auto family support
...
Some IPs like JESD link layer were marked as not supported on Versal devices by
the current flow while other not (e.g. TPL).
The auto family support seems to workaround this issue.
2021-10-05 14:09:51 +03:00